Browsing by Author "Son, Yunik"

A low-power HKMG CMOS platform compatible with DRAM node 2x and beyond

A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies

Assessment of SiGe quantum well transistors for DRAM peripheral applications

Diffusion and gate replacement: a new gate-first high-k/metal gate CMOS integration scheme suppressing gate height symmetry

I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration

Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors

Impact of thermal budget on the low-frequency noise of DRAM peripheral nMOSFETs

Low-frequency noise analysis of DRAM peripheral transistors with La cap

Low-frequency noise assessment of border traps in Al2O3 capped DRAM peripheral MOSFETs

Strained c:Si0.55Ge0.45 with Embedded e:Si0.75Ge0.25 S/D IFQW SiGe-pFET for DRAM periphery applications

Thermal budget impact on HKMG Al2O3 and La-based stacks for 2x DRAM periphery transistors

Thermal stability and reliability in SiGe pMOSFETs for sub-20nm DRAM applications