Browsing by Author "Steegen, An"
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Publication Analog designer's playground beyond 20nm, is it Circuit Physics or Auto Place&Route?
Oral presentation2013, Symposium on VLSI CircuitsPublication BTI reliability of advanced gate stacks for beyond silicon devices: challenges and opportunities
Proceedings paper2014-12, International Electron Device Meeting - IEDM, 15/12/2014, p.828-831Publication Characterisation of the local stress in CoSi2 silicided shallow trench isolation structures
Proceedings paper2001, Microscopy of Semiconducting Materials - MSMXII, 25/03/2001, p.481-484Publication Characterization of the local mechanical stress induced during the Ti and Co/Ti salicidation in sub-0.25μm technologies
Journal article1999, J. Appl. Phys., (86) 8, p.4290-4297Publication Characterization of the Mechanical Stress induced during Silicidation in sub-0.25μm MOS Technologies
Steegen, AnPHD thesis2001-01Publication Control and impact of processing ambient during rapid thermal silicidation
Proceedings paper1998, Rapid and Contact Integrated Processing VII, 13/04/1998, p.297-306Publication Design technology co-optimization for N10
Proceedings paper2014, IEEE Proceedings of the Custom Integrated Circuits Conference - CICC, 15/09/2014, p.1-8Publication Dual-channel technology with Cap-free single metal gate for high performance CMOS in gate-first and gate-last integration
Proceedings paper2011, IEEE International Electron Devices Meeting - IEDM, 5/12/2011, p.654-657Publication Electrical performance and scalability of Ni-monosilicide towards sub 0.13 μm technologies
Oral presentation2001, Symposium K of the MRS Spring Meeting: Gate Stack and Silicide Issues in Si Processing II; 16-20 April 2001; San Francisco, CA,Publication Extreme scaling enabled by 5 tracks cells : holistic design-device co-optimization for FinFETs and lateral nanowires
Proceedings paper2016, IEEE International Electron Devices Meeting - IEDM, 3/12/2016, p.687-690Publication Finite element simulations of the mechanical stress in and around TiSi2 lines
Proceedings paper1998, Micromechanical Structures for Materials Research, 15/04/1998, p.227-232Publication Group IV channels for 7nm FinFETs: Performance for SoCs power and speed metrics
Proceedings paper2014, Symposium on VLSI Technology, 9/06/2014, p.1-2Publication Heterogeneous nano- to wide-scale co-integration of beyond-Si and Si CMOS devices to enhance future electronics
Proceedings paper2015, Silicon Compatible Materials, and Technologies for Advanced Integrated Processes, Circuits and Emerging Applications 5, 29/06/2015, p.3-14Publication High performance Si.45Ge.55 implant free quantum well FET featuring low temperature process, eSiGe stressor and transversal strain relaxation
Proceedings paper2011, IEEE International Electron Devices Meeting - IEDM, 5/12/2011, p.829-832Publication Holisitic device exploration for 7nm node
Proceedings paper2015, IEEE Custom Integrated Circuits Conference - CICC, 20/09/2015, p.1-5Publication Impact of Fin height variations on SRAM yield
Proceedings paper2012-04, International Symposium on VLSI Technology, Systems and Applications - VLSI-TSA, 23/04/2012, p.1-2Publication In situ transmission electron microscopy study of Ni silicide phases formed on (001) Si active lines
; ; Van Landuyt, J.Journal article2001, Journal of Applied Physics, (90) 1, p.167-174Publication In situ transmission electron microscopy study of the silicidation process in Co thin films on patterned (001) Si substrates
Journal article2001, Journal of Materials Research, (16) 3, p.701-708Publication Influence of the As and BF2 junction implantation on the stress induced defects during the Ti- and Co/Ti-silicidation
Proceedings paper1999, Advanced Interconnects and Contacts, 5/04/1999, p.15-22