Browsing by Author "Suhard, Samuel"
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Publication 2 μm Pitch Direct Die-To-Wafer Hybrid Bonding Using Surface Protection During Wafer Thinning And Die Singulation
Proceedings paper2025, 2025 IEEE 75TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC, 2025-05-27, p.272Publication 3D integration challenges for fine pitch back side micro-bumping on ZoneBOND™ wafers
Proceedings paper2012, 4th Electronics System Integration Technologies Conference - ESTC, 17/09/2012Publication 3D stacking cobalt and nickel microbumps and kinetics of corresponding IMCs at low temperatures
Proceedings paper2017, IEEE International Interconnect Technology Conference - IITC, 16/05/2017, p.1-3Publication 3D stacking using bump-less process for sub 10μm pitches
Proceedings paper2016, IEEE 66th Electronic Components and Technology Conference - ECTC, 31/05/2016, p.128-133Publication A record GmSAT/SSSAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation
Proceedings paper2019, 2019 Symposia on VLSI Technology and Circuits, 9/06/2019, p.T92-T93Publication Acoustic modulation during laser debonding of collective hybrid bonded dies
Proceedings paper2021, IEEE 71st Electronic Components and Technology Conference (ECTC), JUN 01-JUL 04, 2021, p.2126-2133Publication Advanced dicing technologies for combination of wafer to wafer and collective die to wafer fusion bonding
Proceedings paper2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 28/05/2018, p.437Publication All-wet removal of post-etch photoresist and sidewall residues: Electrical characterization of 90 nm and 30 nm ½ pitch structures
Meeting abstract2010, SEMATECH Surface Preparation and Cleaning Conference, 22/03/2010Publication Carrier Systems for Collective Die-to-Wafer Bonding
Proceedings paper2022, 72nd IEEE Electronic Components and Technology Conference (ECTC), MAY 31-JUN 01, 2022, p.2058-2063Publication Challenges and Mitigations of Microbumps Pitch Scaling for Chiplet Applications
Journal article2026, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, (16) 1, p.231-243Publication Challenges and novel approaches for photo resist removal and post-etch residue removal for 22 nm interconnects
Proceedings paper2009, IEEE International Interconnect Technology Conference - IITC, 1/06/2009, p.237-239Publication Characterization of low-k dielectric etch residue on the sidewall by chemical force microscope
Meeting abstract2010, 10th International Symposium on Ultra-Clean Processing of Semiconductor Devices - UCPSS, 19/10/2010, p.46-47Publication Cost efficient Infrared Laser debonding technology enabled by Si carrier reuse
Proceedings paper2025, IEEE 27th Electronics Packaging Technology Conference (EPTC), 2025-12-02, p.1-5Publication Demonstration of a collective hybrid die-to-wafer integration
Proceedings paper2020, 70th IEEE Electronic Components and Technology Conference (ECTC), JUN 03-30, 2020, p.1315-1321Publication Demonstration of a collective hybrid die-to-wafer integration using glass carrier
Proceedings paper2021, IEEE 71st Electronic Components and Technology Conference (ECTC), JUN 01-JUL 04, 2021, p.2064-2070Publication Development of a wet silicon removal process for replacement metal gate and sacrificial fin
; ; ; ; Publication Development of a wet silicon removal process for replacement metal gate and sacrificial fin
; ; ; ; Publication Development of an all-in one wet single wafer process for 3D-SIC bump integration and its monitoring
Proceedings paper2016, IEEE 18th Electronics Packaging Technology Conference - EPTC, 30/11/2016, p.107-110Publication Development of integrated wet cleans for 3D-SIC technologies
Proceedings paper2013, Ultra Clean Processing of Semiconductor Surfaces XI - UCPSS, 17/09/2012, p.150-153Publication Die to wafer 3D stacking for below 10μm pitch microbumps
Proceedings paper2016, IEEE International Conference on 3D System Integration - 3DIC, 9/11/2016, p.1-4
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