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Browsing by Author "Tang, Fu"

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    A new quality metric for III-V/high-k MOS gate stacks based on the frequency dispersion of accumulation capacitance and the CET

    Vais, Abhitosh  
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    Franco, Jacopo  
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    Martens, Koen  
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    Lin, Dennis  
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    Sioncke, Sonja
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    Putcha, Vamsi  
    Journal article
    2017, IEEE Electron Device Letters, (38) 3, p.318-321
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    Atomic layer deposition of novel interface layers on III-V channel devices

    Tang, Fu
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    Jiang, Xiaoqiang
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    Xie, Qi  
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    Givens, Michael  
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    Maes, Jan  
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    Sioncke, Sonja
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    Ivanov, Tsvetan  
    Proceedings paper
    2017, AVS 17th International Conference on Atomic Layer Deposition - ALD, 15/07/2017, p.AA2-TuA8
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    BTI Reliability of InGaAs nMOS gate-stack: on the impact of shallow and deep defect bands on the operating voltage range of III-V technology

    Putcha, Vamsi  
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    Franco, Jacopo  
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    Vais, Abhitosh  
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    Sioncke, Sonja
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    Kaczer, Ben  
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    Xie, Qi  
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    Calka, Pauline  
    Proceedings paper
    2017, IEEE International Reliability Physics Symposium - IRPS, 2/04/2017, p.XT-8.1-XT-8.6
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    Engineering the IIIV gate stack properties by optimization of the ALD process

    Sioncke, Sonja
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    Ivanov, Tsvetan  
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    Lin, Dennis  
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    Franco, Jacopo  
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    Vais, Abhitosh  
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    Ameen, Mahmoud
    Meeting abstract
    2014, 226th ECS Fall Meeting, 5/10/2014, p.1613
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    Extensive assessment of the charge-trapping kinetics in InGaAs MOS gate-stacks for the demonstration of improved BTI reliability

    Putcha, Vamsi  
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    Franco, Jacopo  
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    Vais, Abhitosh  
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    Kaczer, Ben  
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    Xie, Qi  
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    Maes, Jan Willem
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    Tang, Fu
    Journal article
    2020, Microelectronics Reliability, 115, p.113996
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    First demonstration of ~3500 cm2/V-s electron mobility and sufficient BTI reliability (max Vov up to 0.6V) In0.53Ga0.47As nFET using an IL/LaSiOx/HfO2 gate stack

    Sioncke, Sonja
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    Franco, Jacopo  
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    Vais, Abhitosh  
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    Putcha, Vamsi  
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    Nyns, Laura  
    Proceedings paper
    2017, Symposium on VLSI Technology, 5/06/2017, p.38-39
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    Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: demonstration of a suitable gate stack for top and bottom tier nMOS

    Franco, Jacopo  
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    Witters, Liesbeth  
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    Vandooren, Anne  
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    Arimura, Hiroaki  
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    Sioncke, Sonja
    Proceedings paper
    2017, IEEE International Reliability Physics Symposium - IRPS, 2/04/2017, p.2B-3.1-2B3.5
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    Novel gate stack engineering for high mobility Ge nFETs

    Arimura, Hiroaki  
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    Cott, Daire  
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    Loo, Roger  
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    Wostyn, Kurt  
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    Boccardi, Guillaume  
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    Franco, Jacopo  
    Meeting abstract
    2018, MRS Spring Meeting, 3/04/2018
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    Si-passivated Ge nMOS gate stack with low DIT and dipole-induced superior PBTI reliability using 3D-compatible ALD caps and high-pressure anneal

    Arimura, Hiroaki  
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    Cott, Daire  
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    Loo, Roger  
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    Vanherle, Wendy  
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    Xie, Qi  
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    Tang, Fu
    ;
    Jiang, Xiaoqiang
    Proceedings paper
    2016, IEEE International Electron Devices Meeting - IEDM, 3/12/2016, p.834-837
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    Temperature dependence of frequency dispersion in III–V metal-oxide-semiconductor C-V and the capture/emission process of border traps

    Vais, Abhitosh  
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    Lin, Dennis  
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    Dou, Chunmeng
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    Martens, Koen  
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    Ivanov, Tsvetan  
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    Xie, Qi  
    ;
    Tang, Fu
    Journal article
    2015, Applied Physics Letters, (107) 5, p.53504

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