Browsing by Author "Yang, Yu"
- Results per page
- Sort Options
Publication Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performances
Proceedings paper2010, IEEE International Electron Devices Meeting - IEDM, 6/12/2010, p.26-29Publication Detection of failure sites by focused ion beam and nano-probing in the interconnect of three-dimensional stacked circuit structures
Journal article2008, Microelectronics Reliability, (48) 8_9, p.1517-1520Publication Extraction of the appropriate material property for realistic modeling of through-silicon-vias using μ-raman spectroscopy
Proceedings paper2008, 11th International Interconnect Technology Conference - IITC, 1/06/2008, p.16-18Publication Impact of thinning and packaging on a deep sub-micron CMOS product
; Yang, YuOral presentation2009, Design, Automation & Test in Europe Conference -DATE : Workshop on 3D Integration (W5)Publication Impact of thinning and through silicon via proximity on high-k / metal gate first CMOS performance
Proceedings paper2010, IEEE Symposium on VLSI Technology, 15/06/2010, p.109-110Publication Process characterization and reliability issues of three dimension-stacked integrated circuit (3D-SIC) structures
Yang, YuPHD thesis2010-11Publication Process induced sub-surface damage in mechanically ground silicon wafers
; ; Publication Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures
; ; ; Travaly, YoussefJournal article2010, Microelectronics Reliability, (50) 9_11, p.1636-1640Publication Statistical analysis of the influence of thinning processes on the strength of silicon
Proceedings paper2009, Materials Technology for 3-D Integration, 1/12/2008, p.1112-E03-09Publication Test structures for characterization of thermal-mechanical stress in 3D stacked IC for analog design
Proceedings paper2010, 23rd IEEE International Conference on Microelectronic Test Structures - ICMTS, 22/03/2010, p.140-144Publication The impact of back-side Cu contamination on 3D stacking architecture
; ; ;