Browsing by author "Loo, Roger"
Now showing items 1-20 of 762
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15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process
Mitard, Jerome; Witters, Liesbeth; Loo, Roger; Lee, Seung Hun; Sun, J.W.; Franco, Jacopo; Ragnarsson, Lars-Ake; Brand, A.; Lu, X.; Yoshido, N.; Eneman, Geert; Brunco, David; Vorderwestner, M.; Storck, P.; Milenin, Alexey; Hikavyy, Andriy; Waldron, Niamh; Favia, Paola; Vanhaeren, Danielle; Vanderheyden, Annelies; Richard, Olivier; Mertens, Hans; Arimura, Hiroaki; Sioncke, Sonja; Vrancken, Christa; Bender, Hugo; Eyben, Pierre; Barla, Kathy; Lee, Sun Ghil; Horiguchi, Naoto; Collaert, Nadine; Thean, Aaron (2014) -
1mA/μm-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D
Mitard, Jerome; Witters, Liesbeth; Hellings, Geert; Krom, Raymond; Franco, Jacopo; Eneman, Geert; Hikavyy, Andriy; Vincent, Benjamin; Loo, Roger; Favia, Paola; Dekkers, Harold; Altamirano Sanchez, Efrain; Vanderheyden, Annelies; Vanhaeren, Danielle; Eyben, Pierre; Takeoka, Shinji; Yamaguchi, Shinpei; Van Dal, Mark; Wang, Wei-E; Hong, Sug-Hun; Vandervorst, Wilfried; De Meyer, Kristin; Biesemans, Serge; Absil, Philippe; Horiguchi, Naoto; Hoffmann, Thomas Y. (2011) -
200mm CVD grown Si/SiGe resonant interband tunnel diodes optimized for high peak-to-valley current ratios
Ramesh, Anisha; Berger, Paul; Douhard, Bastien; Vandervorst, Wilfried; Loo, Roger (2012-06) -
200mm Si/SiGe resonant interband tunneling diodes incorporating delta-doping layers grown by CVD
Park, Si-Young; Anisha, R.; Berger, Paul; Loo, Roger; Nguyen, Duy; Takeuchi, Shotaro; Caymax, Matty (2009) -
25% drive current improvement for p-type Multiple Gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions
Verheyen, Peter; Collaert, Nadine; Rooyackers, Rita; Loo, Roger; Shamiryan, Denis; De Keersgieter, An; Eneman, Geert; Leys, Frederik; Dixit, Abhisek; Goodwin, Michael; Yim, Yong Sik; Caymax, Matty; De Meyer, Kristin; Absil, Philippe; Jurczak, Gosia; Biesemans, Serge (2005) -
50 nm high performance strained Si/SiGe pMOS devices with multiple quantum wells
Collaert, Nadine; Verheyen, Peter; De Meyer, Kristin; Loo, Roger; Caymax, Matty (2002) -
50Gb/s C-band GeSi waveguide electro-absorption modulator
Srinivasan, Ashwyn; Verheyen, Peter; Loo, Roger; De Wolf, Ingrid; Pantouvaki, Marianna; Lepage, Guy; Balakrishnan, Sadhishkumar; Vanherle, Wendy; Absil, Philippe; Van Campenhout, Joris (2016) -
60Gb/s waveguide-coupled O-band GeSi quantum-confined Stark effect electro-absorption modulator
Srinivasan, Ashwyn; Porret, Clément; Balakrishnan, Sadhishkumar; Ban, Yoojin; Loo, Roger; Verheyen, Peter; Van Campenhout, Joris; Pantouvaki, Marianna (2021) -
85nm-wide 1.5mA/μm-ION IFQW SiGe-pFET: raised vs embedded Si0.75Ge0.25 S/D benchmarking and in-depth hole transport study
Mitard, Jerome; Witters, Liesbeth; Eneman, Geert; Hellings, Geert; Pantisano, Luigi; Hikavyy, Andriy; Loo, Roger; Eyben, Pierre; Horiguchi, Naoto; Thean, Aaron (2012) -
8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS
Witters, Liesbeth; Takeoka, Shinji; Yamaguchi, Shinpei; Hikavyy, Andriy; Shamiryan, Denis; Cho, Moon Ju; Chiarella, Thomas; Ragnarsson, Lars-Ake; Loo, Roger; Kerner, Christoph; Crabbe, Yvo; Franco, Jacopo; Tseng, Joshua; Wang, Wei-E; Rohr, Erika; Schram, Tom; Richard, Olivier; Bender, Hugo; Biesemans, Serge; Absil, Philippe; Hoffmann, Thomas Y. (2010) -
A 0.35µm BiCMOS process with selective epitaxial SiGe bipolar transistors
Kuhn, Rudiger; Decoutere, Stefaan; Caymax, Matty; Vleugels, Frank; Verschooten, Eric; Loo, Roger; Loheac, J. L. (1999) -
A 0.35μm SiGe BiCMOS process featuring a 80 GHz Fmax HBT and integrated high-Q RF passive components
Decoutere, Stefaan; Vleugels, Frank; Kuhn, Rudiger; Loo, Roger; Caymax, Matty; Jenei, Snezana; Croon, Jeroen; Van Huylenbroeck, Stefaan; Da Rold, Martina; Rosseel, Erik; Chevalier, P.; Coppens, P. (2000) -
A 2nd generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs
Mitard, Jerome; Witters, Liesbeth; Sasaki, Yuichiro; Arimura, Hiroaki; Schulze, Andreas; Loo, Roger; Ragnarsson, Lars-Ake; Hikavyy, Andriy; Cott, Daire; Chiarella, Thomas; Kubicek, Stefan; Mertens, Hans; Ritzenthaler, Romain; Vrancken, Christa; Favia, Paola; Bender, Hugo; Horiguchi, Naoto; Barla, Kathy; Mocuta, Dan; Mocuta, Anda; Collaert, Nadine; Thean, Aaron (2016-06) -
A 50 nm vertical Si0.70/Ge0.30/Si0.85/Ge0.15 pMOSFET with an oxide/nitride gate dielectric
Verheyen, Peter; Collaert, Nadine; Caymax, Matty; Loo, Roger; Van Rossum, Marc; De Meyer, Kristin (2001) -
A 50nm high-k poly silicon gate stack with a buried SiGe channel
Jakschik, S.; Hoffmann, Thomas Y.; Cho, Hag-Ju; Veloso, Anabela; Loo, Roger; Hyun, S.; Sorada, H.; Inoue, A.; de Potter de ten Broeck, Muriel; Eneman, Geert; Severi, Simone; Absil, Philippe; Biesemans, Serge (2007) -
A 70nm vertical Si/Si1-xGex heterojunction pMOSFET with reduced DIBL sensitivity for VLSI applications
Verheyen, Peter; Collaert, Nadine; Caymax, Matty; Loo, Roger; De Meyer, Kristin; Van Rossum, Marc (1999) -
A demonstration of donor passivation through direct formation of V-Asx complexes in GexSn1-x
Khanam, Afrina; Vohra, Anurag; Slotte, Jonatan; Makkonen, Ilja; Loo, Roger; Pourtois, Geoffrey; Vandervorst, Wilfried (2020-05) -
A model of threading dislocation density in strain-relaxed Ge and GaAs epitaxial films on Si (100)
Wang, Gang; Loo, Roger; Simoen, Eddy; Souriau, Laurent; Caymax, Matty; Heyns, Marc; Blanpain, Bart (2009-03) -
A new complementary hetero-junction vertical tunnel-FET integration scheme
Rooyackers, Rita; Vandooren, Anne; Verhulst, Anne; Walke, A.; Devriendt, Katia; Locorotondo, Sabrina; Demand, Marc; Bryce, George; Loo, Roger; Hikavyy, Andriy; Vandeweyer, Tom; Huyghebaert, Cedric; Collaert, Nadine; Thean, Aaron (2013) -
A new method to fabricate Ge nanowires: selective lateral etching of GeSn:P-Ge multi-stacks
Porret, Clément; Vohra, Anurag; Sebaai, Farid; Douhard, Bastien; Hikavyy, Andriy; Loo, Roger (2018)