Browsing by author "Huynh Bao, Trong"
Now showing items 1-20 of 26
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12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices
Kim, Min-Soo; Harada, N.; Kikuchi, Yoshiaki; Boemmels, Juergen; Mitard, Jerome; Huynh Bao, Trong; Matagne, Philippe; Tao, Zheng; Li, Waikin; Devriendt, Katia; Ragnarsson, Lars-Ake; Lorant, Christophe; Sebaai, Farid; Porret, Clément; Rosseel, Erik; Dangol, Anish; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Geypen, Jef; Jourdan, Nicolas; Sepulveda Marquez, Alfonso; Puliyalil, Harinarayanan; Jamieson, Geraldine; van der Veen, Marleen; Teugels, Lieve; El-Mekki, Zaid; Altamirano Sanchez, Efrain; Li, Y.; Nakamura, H.; Mocuta, Dan; Matsuoka, F. (2019) -
A comprehensive benchmark and optimization of 5-nm lateral and vertical GAA 6T-SRAMs
Huynh Bao, Trong; Sakhare, Sushil; Yakimets, Dmitry; Ryckaert, Julien; Thean, Aaron; Mercha, Abdelkarim; Verkest, Diederik; Wambacq, Piet (2016) -
Challenges and opportunities for vertical nanowire FETs: device design and fabrication
Veloso, Anabela; Matagne, Philippe; Huynh Bao, Trong; Eneman, Geert; Loo, Roger; Wostyn, Kurt; Brus, Stephan; Boemmels, Juergen; Mocuta, Dan; Ryckaert, Julien (2018) -
Challenges and opportunities of vertical FET devices using 3D circuit design layouts
Veloso, Anabela; Huynh Bao, Trong; Rosseel, Erik; Paraschiv, Vasile; Devriendt, Katia; Vecchio, Emma; Delvaux, Christie; Chan, BT; Ercken, Monique; Tao, Zheng; Li, Waikin; Altamirano Sanchez, Efrain; Versluijs, Janko; Brus, Stephan; Matagne, Philippe; Waldron, Niamh; Ryckaert, Julien; Mocuta, Dan; Collaert, Nadine (2016) -
Challenges on surface conditioning in 3D device architectures: triple-gate FinFETs, gate-all-around lateral and vertical nanowire FETs
Veloso, Anabela; Paraschiv, Vasile; Vecchio, Emma; Devriendt, Katia; Li, Waikin; Simoen, Eddy; Chan, BT; Tao, Zheng; Rosseel, Erik; Loo, Roger; Milenin, Alexey; Kunert, Bernardette; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; van Dorp, Dennis; Altamirano Sanchez, Efrain; Brus, Stephan; Marien, Philippe; Fleischmann, Claudia; Melkonyan, Davit; Huynh Bao, Trong; Eneman, Geert; Hellings, Geert; Sibaja-Hernandez, Arturo; Matagne, Philippe; Waldron, Niamh; Mocuta, Dan; Collaert, Nadine (2017) -
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies
Huynh Bao, Trong; Yakimets, Dmitry; Ryckaert, Julien; Ciofi, Ivan; Baert, Rogier; Veloso, Anabela; Boemmels, Juergen; Collaert, Nadine; Roussel, Philippe; Demuynck, Steven; Raghavan, Praveen; Mercha, Abdelkarim; Tokei, Zsolt; Verkest, Diederik; Thean, Aaron; Wambacq, Piet (2014-09) -
Cross-layer design and analysis of al ow power, high density STT-MRAM for embedded systems
Perumkunnil, Manu; Sakhare, Sushil; Huynh Bao, Trong; Rao, Siddharth; Kim, Woojin; Tenllado, Christian; Gomez, Jose Ignacio; Kar, Gouri Sankar; Furnemont, Arnaud; Catthoor, Francky (2017) -
Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM
Huynh Bao, Trong; Sakhare, Sushil; Ryckaert, Julien; Yakimets, Dmitry; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron; Wambacq, Piet (2015) -
DTCO and TCAD for a 12 layer-EUV ultra-scaled surrounding gate transistor 6T-SRAM
Matagne, Philippe; Nakamura, H.; Kim, Min-Soo; Kikuchi, Yoshiaki; Huynh Bao, Trong; Tao, Zheng; Li, Waikin; Devriendt, Katia; Ragnarsson, Lars-Ake; Boemmels, Juergen; Mallik, Arindam; Altamirano Sanchez, Efrain; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Porret, Clément; Mocuta, Dan; Harada, N.; Matsuoka, F. (2018) -
Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node
Sakhare, Sushil; Perumkunnil, Manu; Huynh Bao, Trong; Rao, Siddharth; Kim, Woojin; Crotti, Davide; Yasin, Farrukh; Couet, Sebastien; Swerts, Johan; Kundu, Shreya; Yakimets, Dmitry; Baert, Rogier; Oh, Hyungrock; Spessot, Alessio; Mocuta, Anda; Kar, Gouri Sankar; Furnemont, Arnaud (2018) -
Gate-All-Around nanowire & nanosheet FETs for advanced, ultra-scaled technologies (Keynote)
Veloso, Anabela; Matagne, Philippe; Jang, Doyoung; Huynh Bao, Trong; Vaisman Chasin, Adrian; Simoen, Eddy; Eneman, Geert; De Keersgieter, An; Mertens, Hans; Horiguchi, Naoto (2020) -
Heterogeneous nano- to wide-scale co-integration of beyond-Si and Si CMOS devices to enhance future electronics
Thean, Aaron; Collaert, Nadine; Radu, Iuliana; Waldron, Niamh; Merckling, Clement; Witters, Liesbeth; Loo, Roger; Mitard, Jerome; Rooyackers, Rita; Vandooren, Anne; Verhulst, Anne; Veloso, Anabela; Yakimets, Dmitry; Huynh Bao, Trong; Chiappe, Daniele; Vaysset, Adrien; Zografos, Odysseas; Caymax, Matty; Huyghebaert, Cedric; Barla, Kathy; Steegen, An (2015) -
Heterogeneous nano-electronic devices enabled by monolithic integration of IIIV, Ge, and Si to expand future CMOS functionality
Thean, Aaron; Collaert, Nadine; Waldron, Niamh; Merckling, Clement; Witters, Liesbeth; Loo, Roger; Mitard, Jerome; Rooyackers, Rita; Vandooren, Anne; Verhulst, Anne; Veloso, Anabela; Pourghaderi, Mohammad Ali; Eneman, Geert; Yakimets, Dmitry; Huynh Bao, Trong; Garcia Bardon, Marie; Ryckaert, Julien; Dehan, Morin; Wambacq, Piet; Caymax, Matty (2014) -
Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells
Veloso, Anabela; Parvais, Bertrand; Matagne, Philippe; Simoen, Eddy; Huynh Bao, Trong; Paraschiv, Vasile; Vecchio, Emma; Devriendt, Katia; Rosseel, Erik; Ercken, Monique; Chan, BT; Delvaux, Christie; Altamirano Sanchez, Efrain; Versluijs, Janko; Tao, Zheng; Suhard, Samuel; Brus, Stephan; Sibaja-Hernandez, Arturo; Waldron, Niamh; Lagrain, Pieter; Richard, Olivier; Bender, Hugo; Vaisman Chasin, Adrian; Kaczer, Ben; Ivanov, Tsvetan; Ramesh, Siva; De Meyer, Kristin; Ryckaert, Julien; Collaert, Nadine; Thean, Aaron (2016) -
Lateral versus vertical gate-all-around FETs for beyond 7nm technologies
Yakimets, Dmitry; Huynh Bao, Trong; Garcia Bardon, Marie; Dehan, Morin; Collaert, Nadine; Mercha, Abdelkarim; Tokei, Zsolt; Thean, Aaron; Verkest, Diederik; De Meyer, Kristin (2014) -
Nanowire & nanosheet FETs for ultra-scaled, hgh-density logic and memory applications
Veloso, Anabela; Huynh Bao, Trong; Matagne, Philippe; Jang, Doyoung; Eneman, Geert; Horiguchi, Naoto; Ryckaert, Julien (2020) -
Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications
Veloso, Anabela; Huynh Bao, Trong; Matagne, Philippe; Jang, Doyoung; Horiguchi, Naoto; Ryckaert, Julien; Mocuta, Dan (2019) -
Process, circuit and system co-optimization of wafer level co-integrated FinFET with vertical nanosheet selector for STT-MRAM applications
Huynh Bao, Trong; Veloso, Anabela; Matagne, Philippe; Ryckaert, Julien; Crotti, Davide; Yasin, Farrukh; Perumkunnil, Manu; Spessot, Alessio; Kar, Gouri Sankar; Mocuta, Anda; Furnemont, Arnaud (2019) -
SRAM designs for 5nm node and beyond: opportunities and challenges
Huynh Bao, Trong; Sakhare, Sushil; Ryckaert, Julien; Spessot, Alessio; Verkest, Diederik; Mocuta, Anda (2017) -
Statistical timing analysis considering device and interconnect variability for BEOL requirements in the 5-nm node and beyond
Huynh Bao, Trong; Ryckaert, Julien; Tokei, Zsolt; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron (2017-05)