Browsing by author "Mertens, Hans"
Now showing items 41-60 of 121
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Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates
Mertens, Hans; Ritzenthaler, Romain; Hikavyy, Andriy; Kim, Min-Soo; Tao, Zheng; Wostyn, Kurt; Chew, Soon Aik; De Keersgieter, An; Mannaert, Geert; Rosseel, Erik; Schram, Tom; Devriendt, Katia; Tsvetanova, Diana; Dekkers, Harold; Demuynck, Steven; Vaisman Chasin, Adrian; Van Besien, Els; Dangol, Anish; Godny, Stephane; Douhard, Bastien; Bosman, Niels; Richard, Olivier; Geypen, Jef; Bender, Hugo; Barla, Kathy; Mocuta, Dan; Horiguchi, Naoto; Thean, Aaron (2016) -
Gate-All-Around nanosheet field-effect transistors for advanced logic and memory applications: integration and device features
Veloso, Anabela; Matagne, Philippe; Eneman, Geert; Mertens, Hans; Vaisman Chasin, Adrian; Simoen, Eddy; Horiguchi, Naoto (2020) -
Gate-All-Around nanosheet field-effect transistors for advanced logic and memory applications: integration and device features
Veloso, Anabela; Matagne, Philippe; Eneman, Geert; Mertens, Hans; Vaisman Chasin, Adrian; Simoen, Eddy; Horiguchi, Naoto (2020) -
Gate-All-Around nanowire & nanosheet FETs for advanced, ultra-scaled technologies (Keynote)
Veloso, Anabela; Matagne, Philippe; Jang, Doyoung; Huynh Bao, Trong; Vaisman Chasin, Adrian; Simoen, Eddy; Eneman, Geert; De Keersgieter, An; Mertens, Hans; Horiguchi, Naoto (2020) -
Gate-All-Around nanowire & nanosheet FETs for advanced, ultra-scaled technologies (Keynote)
Veloso, Anabela; Matagne, Philippe; Jang, Doyoung; Huynh-Bao, Trong; Vaisman Chasin, Adrian; Simoen, Eddy; Eneman, Geert; De Keersgieter, An; Mertens, Hans; Horiguchi, Naoto (2020) -
Gate-all-around transistors based on vertically stacked Si nanowires
Mertens, Hans; Ritzenthaler, Romain; Hikavyy, Andriy; Kim, Min-Soo; Tao, Zheng; Wostyn, Kurt; Schram, Tom; Kunnen, Eddy; Ragnarsson, Lars-Ake; Dekkers, Harold; Hopf, Toby; Devriendt, Katia; Tsvetanova, Diana; Chew, Soon Aik; Kikuchi, Yoshiaki; Van Besien, Els; Rosseel, Erik; Mannaert, Geert; De Keersgieter, An; Vaisman Chasin, Adrian; Kubicek, Stefan; Dangol, Anish; Demuynck, Steven; Barla, Kathy; Mocuta, Dan; Horiguchi, Naoto (2017) -
Gate-all-around transistors based on vertically stacked Si nanowires: recent progress in CMOS integration and in advanced inline metrology
Mertens, Hans; Ritzenthaler, Romain; Mocuta, Dan; Horiguchi, Naoto (2018) -
Ge nFET with high electron mobility and superior PBTI reliability enabled by monolayer-Si surface passivation and La-induced interface dipole formation
Arimura, Hiroaki; Sioncke, Sonja; Cott, Daire; Mitard, Jerome; Conard, Thierry; Vanherle, Wendy; Loo, Roger; Favia, Paola; Bender, Hugo; Meersschaut, Johan; Witters, Liesbeth; Mertens, Hans; Franco, Jacopo; Ragnarsson, Lars-Ake; Pourtois, Geoffrey; Heyns, Marc; Mocuta, Anda; Collaert, Nadine; Thean, Aaron (2015) -
Germanium for advanced CMOS transistors: status and trends of this technology
Mitard, Jerome; Witters, Liesbeth; Arimura, Hiroaki; Sasaki, Yuichiro; Milenin, Alexey; Loo, Roger; Hikavyy, Andriy; Eneman, Geert; Lagrain, Pieter; Mertens, Hans; Vrancken, Christa; Bender, Hugo; Horiguchi, Naoto; Mocuta, Anda; Collaert, Nadine; Thean, Aaron (2015) -
High Ge content SiGe thin films: growth, properties and integration
Hikavyy, Andriy; Witters, Liesbeth; Mertens, Hans; Bender, Hugo; Favia, Paola; Loo, Roger (2014) -
High Ge content SiGe thin films: growth, properties and integration
Hikavyy, Andriy; Rosseel, Erik; Dhayalan, Sathish Kumar; Witters, Liesbeth; Mertens, Hans; Bender, Hugo; Favia, Paola; Loo, Roger (2014) -
Horizontal, stacked or vertical silicon nanowires: Does it Matter from a Low-Frequency Noise Perspective
Simoen, Eddy; Oliveira, Alberto; Agopian, Paula G der; Ritzenthaler, Romain; Mertens, Hans; Horiguchi, Naoto; Martino, Joao A; Claeys, Cor; Veloso, Anabela (2021) -
Impact of device architecture and gate stack processing on the low-frequency noise of silicon nanowire transistors
Simoen, Eddy; Oliveira, Alberto Vinicius; Veloso, Anabela; Vaisman Chasin, Adrian; Ritzenthaler, Romain; Mertens, Hans; Horiguchi, Naoto; Claeys, Cor (2019) -
Impact of gate stack dielectric on intrinsic voltage gain and low frequency noise in Ge pMOSFETs
Oliveira, A.V.; Agopian, P.G.D.; Martino, J.A.; Fang, Wen; Arimura, Hiroaki; Mitard, Jerome; Mertens, Hans; Simoen, Eddy; Mocuta, Anda; Collaert, Nadine; Thean, Aaron; Claeys, Cor (2015) -
Impact of gate stack layer composition on dynamic threshold voltage and analog parameters of Ge pMOSFETs
Vinicius de Oliveira, Alberto; Agopian, G.D.; Martino, J.; Simoen, Eddy; Claeys, Cor; Mertens, Hans; Collaert, Nadine; Thean, Aaron (2016) -
Inspection and metrology challenges for 3 nm node devices and beyond
Shohjoh, T.; Ikota, M.; Isawa, M.; Lorusso, Gian; Horiguchi, Naoto; Briggs, Basoene; Mertens, Hans; Bogdanowicz, Janusz; De Bisschop, Peter; Charley, Anne-Laure (2021) -
Investigating Nanowire, Nanosheet and Forksheet FET Hot-Carrier Reliability via TCAD Simulations
Vandemaele, Michiel; Kaczer, Ben; Bury, Erik; Franco, Jacopo; Vaisman Chasin, Adrian; Makarov, Alexander; Mertens, Hans; Hellings, Geert; Groeseneken, Guido (2023-05-15) -
Isolation of nanowires made on bulk wafers by ground plane doping
Ritzenthaler, Romain; Mertens, Hans; De Keersgieter, An; Mitard, Jerome; Mocuta, Dan; Horiguchi, Naoto (2017) -
Isotropic Etches to Enable Forksheet FET Integration
Oniki, Yusuke; Mertens, Hans; Puttarame Gowda, Pallavi; Sebaai, Farid; Altamirano Sanchez, Efrain; Holsteyns, Frank; Horiguchi, Naoto (2021) -
Junction technology challenges and solutions for 3D device architecture
Kikuchi, Yoshiaki; Mertens, Hans; Ritzenthaler, Romain; Chiarella, Thomas; Peter, Antony; Horiguchi, Naoto (2019)