Browsing by author "Demand, Marc"

45nm nMOSFET with metal gate on thin SiON driving 1150μA/μm and off-state of 10nA/μm

Henson, Kirklen; Lander, Rob; Demand, Marc; Dachs, Charles; Kaczer, Ben; Deweerd, Wim; Schram, Tom; Tokei, Zsolt; Hooker, Jacob; Cubaynes, Florence; Beckx, Stephan; Boullart, Werner; Coenegrachts, Bart; Vertommen, Johan; Richard, Olivier; Bender, Hugo; Vandervorst, Wilfried; Kaiser, M.; Everaert, Jean-Luc; Jurczak, Gosia; Biesemans, Serge (2004)

A 35nm diameter vertical silicon nanowire short-gate tunnelFET

Vandooren, Anne; Rooyackers, Rita; Leonelli, Daniele; Iacopi, Francesca; De Gendt, Stefan; Verhulst, Anne; Heyns, Marc; Kunnen, Eddy; Nguyen, Duy; Demand, Marc; Ong, Patrick; Lee, Willie; Moonens, Jos; Richard, Olivier; Vandenberghe, William; Groeseneken, Guido (2009)

A fully planar stacked gate flash technology with T-shaped floating gate for increased cell coupling ratio

De Vos, Joeri; Haspeslagh, Luc; Blomme, Pieter; Demand, Marc; Devriendt, Katia; Vleugels, Frank; Wellekens, Dirk; Van Houdt, Jan (2007)

A new complementary hetero-junction vertical tunnel-FET integration scheme

Rooyackers, Rita; Vandooren, Anne; Verhulst, Anne; Walke, A.; Devriendt, Katia; Locorotondo, Sabrina; Demand, Marc; Bryce, George; Loo, Roger; Hikavyy, Andriy; Vandeweyer, Tom; Huyghebaert, Cedric; Collaert, Nadine; Thean, Aaron (2013)

Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack

Veloso, Anabela; Yu, HongYu; Lauwers, Anne; Chang, Shou-Zen; Adelmann, Christoph; Onsia, Bart; Demand, Marc; Brus, Stephan; Vrancken, Christa; Singanamalla, Raghunath; Lehnen, Peer; Kittl, Jorge; Kauerauf, Thomas; Vos, Rita; O'Sullivan, Barry; Van Elshocht, Sven; Mitsuhashi, Riichirou; Whittemore, G.; Yin, K.M.; Niwa, Masaaki; Hoffmann, Thomas; Absil, Philippe; Jurczak, Gosia; Biesemans, Serge (2007-09)

Achieving low-VT Ni-FUSI CMOS via Lanthanide incorporation in the gate stack

Veloso, Anabela; Yu, HongYu; Lauwers, Anne; Chang, Shou-Zen; Adelmann, Christoph; Onsia, Bart; Demand, Marc; Brus, Stephan; Vrancken, Christa; Singanamalla, Raghunath; Lehnen, Peer; Kittl, Jorge; Kauerauf, Thomas; Vos, Rita; O'Sullivan, Barry; Van Elshocht, Sven; Mitsuhashi, Riichirou; Whittemore, G.; Yin, K.M.; Niwa, Masaaki; Hoffmann, Thomas; Absil, Philippe; Jurczak, Gosia; Biesemans, Serge (2008)

Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction tunnel-FETs

Vandooren, Anne; Rooyackers, Rita; Leonelli, Daniele; Hikavyy, Andriy; Devriendt, Katia; Demand, Marc; Loo, Roger; Groeseneken, Guido; Huyghebaert, Cedric (2013)

Capping-metal gate integration technology for multiple-VT CMOS in MuGFETs

Veloso, Anabela; Witters, Liesbeth; Demand, Marc; Ferain, Isabelle; Son, Nak Jin; Kaczer, Ben; Roussel, Philippe; Adelmann, Christoph; Brus, Stephan; Richard, Olivier; Bender, Hugo; Conard, Thierry; Vos, Rita; Rooyackers, Rita; Van Elshocht, Sven; Collaert, Nadine; De Meyer, Kristin; Biesemans, Serge; Jurczak, Malgorzata (2008)

Challenges building a 22nm node 6T-SRAM cell using immersion lithography

Ercken, Monique; Altamirano Sanchez, Efrain; Baerts, Christina; Brus, Stephan; De Backer, Johan; Demand, Marc; Delvaux, Christie; Horiguchi, Naoto; Locorotondo, Sabrina; Vandeweyer, Tom; Veloso, Anabela; Verhaegen, Staf (2009)

Challenges in using optical lithography for the building of a 22 nm node 6T=-SRAM cell

Ercken, Monique; Altamirano Sanchez, Efrain; Baerts, Christina; Brus, Stephan; De Backer, Johan; Delvaux, Christie; Demand, Marc; Horiguchi, Naoto; Locorotondo, Sabrina; Vandeweyer, Tom; Veloso, Anabela; Verhaegen, Staf (2010)

Cost effective low Vt Ni-FUSI CMOS on SiON by means of Al implant (pMOS) and Yb+P implant (nMOS)

Lauwers, Anne; Veloso, Anabela; Chang, Shou-Zen; Yu, HongYu; Hoffmann, Thomas Y.; Kerner, Christoph; Demand, Marc; Rothschild, Aude; Niwa, Masaaki; Satoru, Ito; Mitshashi, Riichirou; Ameen, Mike; Whittemore, Graham; Pawlak, Malgorzata; Vrancken, Christa; Demeurisse, Caroline; Mertens, Sofie; Vandervorst, Wilfried; Absil, Philippe; Biesemans, Serge; Kittl, Jorge (2008)

Demonstration of recessed SiGe S/D and inserted metal gate on HfO2 for high performance pFETs

Verheyen, Peter; Eneman, Geert; Rooyackers, Rita; Loo, Roger; Eeckhout, Lieve; Rondas, Dirk; Leys, Frederik; Snow, Jim; Shamiryan, Denis; Demand, Marc; Hoffmann, Thomas Y.; Goodwin, Michael; Fujimoto, Hiromasa; Ravit, Claire; Lee, Byeong Chan; Caymax, Matty; De Meyer, Kristin; Absil, Philippe; Jurczak, Gosia; Biesemans, Serge (2005-12)

Demonstration of scaled 0.099μm² FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

Veloso, Anabela; Demuynck, Steven; Ercken, Monique; Goethals, Mieke; Locorotondo, Sabrina; Lazzarino, Frederic; Altamirano Sanchez, Efrain; Huffman, Craig; De Keersgieter, An; Brus, Stephan; Demand, Marc; Struyf, Herbert; De Backer, Johan; Hermans, Jan; Delvaux, Christie; Baudemprez, Bart; Vandeweyer, Tom; Van Roey, Frieda; Baerts, Christina; Goossens, Danny; Dekkers, Harold; Ong, Patrick; Heylen, Nancy; Kellens, Kristof; Volders, Henny; Hikavyy, Andriy; Vrancken, Christa; Rakowski, Michal; Verhaegen, Staf; Dusa, Mircea; Romijn, Leon; Pigneret, Charles; van Dijk, Andre; Schreutelkamp, Rob; Cockburn, Andrew; Gravey, Virginie; Meiling, H.; Hultermans, B.; Lok, S.; Shah, K.; Rajagopalan, R.; Gelatos, J.; Richard, Olivier; Bender, Hugo; Vandenberghe, Geert; Beyer, Gerald; Absil, Philippe; Hoffmann, Thomas Y.; Ronse, Kurt; Biesemans, Serge (2009-12)