Browsing by author "De Meyer, Kristin"
Now showing items 1-20 of 444
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0.13µm CMOS technology with optimized poly-Si / NO-oxide gate stack
Kubicek, Stefan; Jansen, Philippe; Badenes, Gonçal; Schaekers, Marc; Kol'dyaev, Victor; Deferm, Ludo; De Meyer, Kristin; Kerr, Daniel; Naem, Abdalla (1999) -
1.5×10-9 Ω·cm² Contact Resistivity on Highly Doped Si:P Using Ge Pre-amorphization and Ti Silicidation
Yu, Hao; Schaekers, Marc; Rosseel, Erik; Peter, Antony; Lee, Joon-Gon; Song, Woo-Bin; Demuynck, Steven; Chiarella, Thomas; Ragnarsson, Lars-Ake; Kubicek, Stefan; Everaert, Jean-Luc; Horiguchi, Naoto; Barla, Kathy; Kim, Daeyong; Collaert, Nadine; Thean, Aaron; De Meyer, Kristin (2015) -
16 QAM burst mode receiver for upstream communication over CATV networks
Codenie, Jan; Wang, X.; Everaert, Alain; Lambrecht, Peter; Vandewege, Jan; De Meyer, Kristin; Trog, W.; De Vleeshouwer, A. (1998) -
1mA/μm-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D
Mitard, Jerome; Witters, Liesbeth; Hellings, Geert; Krom, Raymond; Franco, Jacopo; Eneman, Geert; Hikavyy, Andriy; Vincent, Benjamin; Loo, Roger; Favia, Paola; Dekkers, Harold; Altamirano Sanchez, Efrain; Vanderheyden, Annelies; Vanhaeren, Danielle; Eyben, Pierre; Takeoka, Shinji; Yamaguchi, Shinpei; Van Dal, Mark; Wang, Wei-E; Hong, Sug-Hun; Vandervorst, Wilfried; De Meyer, Kristin; Biesemans, Serge; Absil, Philippe; Horiguchi, Naoto; Hoffmann, Thomas Y. (2011) -
25% drive current improvement for p-type Multiple Gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions
Verheyen, Peter; Collaert, Nadine; Rooyackers, Rita; Loo, Roger; Shamiryan, Denis; De Keersgieter, An; Eneman, Geert; Leys, Frederik; Dixit, Abhisek; Goodwin, Michael; Yim, Yong Sik; Caymax, Matty; De Meyer, Kristin; Absil, Philippe; Jurczak, Gosia; Biesemans, Serge (2005) -
3D stacked IC demonstrator using hybrid collective die-to-wafer bonding with copper through silicon vias (TSV)
Van Olmen, Jan; Coenen, Jens; Dehaene, Wim; De Meyer, Kristin; Huyghebaert, Cedric; Jourdain, Anne; Katti, Guruprasad; Mercha, Abdelkarim; Rakowski, Michal; Stucchi, Michele; Travaly, Youssef; Beyne, Eric; Swinnen, Bart (2009) -
3D stacked ICs using Cu TSVs and die to wafer hybrid collective bonding
Katti, Guruprasad; Mercha, Abdelkarim; Van Olmen, Jan; Huyghebaert, Cedric; Jourdain, Anne; Stucchi, Michele; Rakowski, Michal; Debusschere, Ingrid; Soussan, Philippe; Dehaene, Wim; De Meyer, Kristin; Travaly, Youssef; Beyne, Eric; Biesemans, Serge; Swinnen, Bart (2009) -
50 nm high performance strained Si/SiGe pMOS devices with multiple quantum wells
Collaert, Nadine; Verheyen, Peter; De Meyer, Kristin; Loo, Roger; Caymax, Matty (2002) -
70 nm fully-depleted SOI cmos using a new fabrication scheme: the spacer/replacer scheme
van Meer, Hans; De Meyer, Kristin (2002) -
A 0.314mm2 6T-SRAM cell built with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography
Nackaerts, Axel; Ercken, Monique; Demuynck, Steven; Lauwers, Anne; Baerts, Christina; Bender, Hugo; Boullart, Werner; Collaert, Nadine; Degroote, Bart; Delvaux, Christie; de Marneffe, Jean-Francois; Dixit, Abhisek; De Meyer, Kristin; Hendrickx, Eric; Heylen, Nancy; Jaenen, Patrick; Laidler, David; Locorotondo, Sabrina; Maenhoudt, Mireille; Moelants, Myriam; Pollentier, Ivan; Ronse, Kurt; Rooyackers, Rita; Van Aelst, Joke; Vandenberghe, Geert; Vandervorst, Wilfried; Vandeweyer, Tom; Vanhaelemeersch, Serge; Van Hove, Marleen; Van Olmen, Jan; Verhaegen, Staf; Versluijs, Janko; Vrancken, Christa; Wiaux, Vincent; Jurczak, Gosia; Biesemans, Serge (2004-12) -
A 2-D analytical threshold voltage model for fully-depleted SOI MOSFETs with halos or pockets
van Meer, Hans; De Meyer, Kristin (2001) -
A 2D analytical threshold voltage model for fully depleted short channel SOI MOSFET, inculding HALO
van Meer, Hans; De Meyer, Kristin (2000) -
A 400GHz fMAX fully self-aligned SiGe:C HBT architecture
Van Huylenbroeck, Stefaan; Sibaja-Hernandez, Arturo; Venegas, Rafael; You, Shuzhen; Winderickx, Gillis; Radisic, Dunja; Lee, Willie; Ong, Patrick; Vandeweyer, Tom; Nguyen, Duy; De Meyer, Kristin; Decoutere, Stefaan (2009-10) -
A 4×20Gb/s WDM ring-based hybrid CMOS silicon photonics transceiver
Rakowski, Michal; Pantouvaki, Marianna; De Heyn, Peter; Verheyen, Peter; Ingels, Mark; Chen, Hongtao; De Coster, Jeroen; Lepage, Guy; Snyder, Brad; De Meyer, Kristin; Steyaert, Michiel; Pavarelli, Nicola; Lee, Jun Su; O'Brien, Peter; Absil, Philippe; Van Campenhout, Joris (2015) -
A 50 nm vertical Si0.70/Ge0.30/Si0.85/Ge0.15 pMOSFET with an oxide/nitride gate dielectric
Verheyen, Peter; Collaert, Nadine; Caymax, Matty; Loo, Roger; Van Rossum, Marc; De Meyer, Kristin (2001) -
A 70nm vertical Si/Si1-xGex heterojunction pMOSFET with reduced DIBL sensitivity for VLSI applications
Verheyen, Peter; Collaert, Nadine; Caymax, Matty; Loo, Roger; De Meyer, Kristin; Van Rossum, Marc (1999) -
A CMOS compatible polycrystalline silicon-germanium based piezoresistive pressure sensor
Gonzalez, Pilar; Guo, Bin; Severi, Simone; De Meyer, Kristin; Witvrouw, Ann (2011) -
A consistent model for the SANOS programming operation
Furnemont, Arnaud; Rosmeulen, Maarten; Cacciato, Antonio; Breuil, Laurent; De Meyer, Kristin; Maes, Herman; Van Houdt, Jan (2007) -
A fast and accurate method to study the impact of interface traps on germanium MOS performance
Hellings, Geert; Eneman, Geert; Mitard, Jerome; Martens, Koen; Wang, Wei-E; Hoffmann, Thomas Y.; Meuris, Marc; De Meyer, Kristin (2011) -
A figure of merit for flash memory multi-leyer tunnel dielectrics
Govoreanu, Bogdan; Blomme, Pieter; Rosmeulen, Maarten; Van Houdt, Jan; De Meyer, Kristin (2001)