Browsing by author "Swinnen, Bart"
Now showing items 21-40 of 96
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Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performances
Mercha, Abdelkarim; Van der Plas, Geert; Moroz, V.; De Wolf, Ingrid; Asimakopoulos, Panagiotis; Minas, Nikolaos; Domae, Shinichi; Perry, Dan; Choi, M.; Redolfi, Augusto; Okoro, Chukwudi; Yang, Yu; Van Olmen, Jan; Thangaraju, Sarasvathi; Sabuncuoglu Tezcan, Deniz; Soussan, Philippe; Cho, Jong Hoon; Yakovlev, A.; Marchal, Pol; Travaly, Youssef; Beyne, Eric; Biesemans, Serge; Swinnen, Bart (2010) -
Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology
Guo, Wei; Moroz, Victor; Van der Plas, Geert; Choi, M.; Redolfi, Augusto; Smith, L.; Eneman, Geert; Van Huylenbroeck, Stefaan; Su, P.D.; Ivankovic, Andrej; De Wachter, Bart; Debusschere, Ingrid; Croes, Kris; De Wolf, Ingrid; Mercha, Abdelkarim; Beyer, Gerald; Swinnen, Bart; Beyne, Eric (2013) -
Copper-nail TSV technology for 3D-stacked IC integration
Snoeckx, Koen; Beyne, Eric; Swinnen, Bart (2007-05) -
Cost-effective 3D-system integration
Swinnen, Bart (2009) -
Cu plating of through-Si vias for 3D-stacked integrated circuits
Radisic, Alex; Luhn, Ole; Swinnen, Bart; Bender, Hugo; Drijbooms, Chris; Doumen, Geert; Kellens, Kristof; Ruythooren, Wouter; Vereecken, Philippe (2008) -
Cu Plating of Through-Si Vias for 3D-Stacked Integrated Circuits
Radisic, Alex; Luhn, Ole; Swinnen, Bart; Bender, Hugo; Drijbooms, Chris; Doumen, Geert; Kellens, Kristof; Ruythooren, Wouter; Vereecken, Philippe (2009) -
Demonstration of ultra-thin Si grinding process controlled by in-situ non-contact gauge for 3D stacked IC (3D-SIC)
Zhao, Ming; Verbinnen, Greet; Yoshida, Shinji; Hayakawa, Susumu; Tabuchi, Tomotaka; Jourdain, Anne; Beyne, Eric; Swinnen, Bart; Leunissen, Peter (2010) -
Detection of failure sites by focused ion beam and nano-probing in the interconnect of three-dimensional stacked circuit structures
Yang, Yu; Bender, Hugo; Arstila, Kai; Swinnen, Bart; Verlinden, Bert; De Wolf, Ingrid (2008) -
Developing underfill process in screening of no-flow underfill and wafer-applied underfill materials for 3D stacking
Rebibis, Kenneth June; Capuz, Giovanni; Daily, Robert; Gerets, Carine; Duval, Fabrice; Wang, Teng; Struyf, Herbert; Miller, Andy; Beyer, Gerald; Beyne, Eric; Swinnen, Bart (2013) -
Direct hybrid bonding
Swinnen, Bart; Jourdain, Anne; De Moor, Piet; Beyne, Eric (2008) -
Electrically yielding collective hybrid bonding for 3D stacking of ICs
Jourdain, Anne; Soussan, Philippe; Swinnen, Bart; Beyne, Eric (2009) -
Electro-migration behavior of Pb-free flip chip bumps
Labie, Riet; Webers, Tomas; Swinnen, Bart; Beyne, Eric (2005) -
Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-Silicon Via Interconnects
Civale, Yann; Armini, Silvia; Philipsen, Harold; Redolfi, Augusto; Velenis, Dimitrios; Croes, Kristof; Heylen, Nancy; El-Mekki, Zaid; Vandersmissen, Kevin; Beyer, Gerald; Swinnen, Bart; Beyne, Eric (2012) -
Evolution of temporary wafer (de)bonding technology towards low temperature processes for enhanced 3D integration
Phommahaxay, Alain; Jourdain, Anne; Bex, Pieter; Van den Eede, Axel; Swinnen, Bart; Beyer, Gerald; Miller, Andy; Beyne, Eric (2012) -
Extraction of the appropriate material property for realistic modeling of through-silicon-vias using μ-raman spectroscopy
Okoro, Chukwudi; Yang, Yu; Vandevelde, Bart; Swinnen, Bart; Vandepitte, Dirk; Verlinden, Bert; De Wolf, Ingrid (2008) -
Grinding and mixed silicon copper CMP of stacked patterned wafers for 3D integration
De Munck, Koen; Vaes, Jan; Bogaerts, Lieve; De Moor, Piet; Van Hoof, Chris; Swinnen, Bart (2007) -
Highly-conformal plasma-enhanced atomic-layer deposition silicon dioxide liner for high aspect-ratio through-silicon via 3D interconnections
Civale, Yann; Redolfi, Augusto; Velenis, Dimitrios; Heylen, Nancy; Beynet, Julien; Jung, Insoo; Woo, Jeong-Jun; Swinnen, Bart; Beyer, Gerald; Beyne, Eric (2012) -
Impact of 3D design choices on manufacturing cost
Velenis, Dimitrios; Stucchi, Michele; Marinissen, Erik Jan; Swinnen, Bart; Beyne, Eric (2009) -
Impact of thinning and through silicon via proximity on high-k / metal gate first CMOS performance
Mercha, Abdelkarim; Redolfi, Augusto; Stucchi, Michele; Minas, Nikolaos; Van Olmen, Jan; Thangaraju, Sarasvathi; Velenis, Dimitrios; Domae, Shinichi; Yang, Yu; Katti, Guruprasad; Labie, Riet; Okoro, Chukwudi; Zhao, Ming; Asimakopoulos, Panagiotis; De Wolf, Ingrid; Chiarella, Thomas; Schram, Tom; Rohr, Erika; Van Ammel, Annemie; Jourdain, Anne; Ruythooren, Wouter; Armini, Silvia; Radisic, Alex; Philipsen, Harold; Heylen, Nancy; Kostermans, Maarten; Jaenen, Patrick; Sleeckx, Erik; Sabuncuoglu Tezcan, Deniz; Debusschere, Ingrid; Soussan, Philippe; Perry, Dan; Van der Plas, Geert; Cho, Jong Hoon; Marchal, Pol; Travaly, Youssef; Beyne, Eric; Biesemans, Serge; Swinnen, Bart (2010) -
Impact of through silicon via induced mechanical stress on fully depleted bulk FinFET technology
Guo, Wei; Van der Plas, Geert; Ivankovic, Andrej; Cherman, Vladimir; Eneman, Geert; De Wachter, Bart; Togo, Mitsuhiro; Redolfi, Augusto; Kubicek, Stefan; Civale, Yann; Chiarella, Thomas; Vandevelde, Bart; Croes, Kristof; De Wolf, Ingrid; Debusschere, Ingrid; Mercha, Abdelkarim; Thean, Aaron; Beyer, Gerald; Swinnen, Bart; Beyne, Eric (2012)