Browsing by author "Wiaux, Vincent"
Now showing items 21-40 of 126
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Characterization of a thermal freeze LLE double patterning process for predictive simulation
Robertson, Stewart; Wong, Patrick; Biafore, John; Vandenbroeck, Nadia; Wiaux, Vincent (2010) -
Checking design conformance and optimizing manufacturability using automated double-patterning decomposition
Cork, Christopher M.; Ward, Brian; Barnes, Levi D.; Painter, Ben; Lucas, Kevin; Luk-Pat, Gerry; Wiaux, Vincent; Verhaegen, Staf; Maenhoudt, Mireille (2008) -
Chromeless phase lithography for contact hole imaging
Vandenberghe, Geert; Hendrickx, Eric; Wiaux, Vincent (2004) -
CMOS 32nm technology node: business as usual for interconnect damascene patterning?
Beyer, Gerald; Ciofi, Ivan; Van Olmen, Jan; Carbonell, Laure; Versluijs, Janko; Wiaux, Vincent; Op de Beeck, Maaike; Maenhoudt, Mireille; Struyf, Herbert; Hendrickx, Dirk; de Marneffe, Jean-Francois; Vereecke, Guy; Claes, Martine; Bearda, Twan; Volders, Henny; Heylen, Nancy; Travaly, Youssef; Stucchi, Michele; Tokei, Zsolt; Cartuyvels, Rudi (2008-12) -
Compact photonic spot-size converter
Luyssaert, Bert; Vandersteegen, Peter; Bogaerts, Wim; Wiaux, Vincent; Wouters, Jan; Baets, Roel (2004) -
Comparisons of 9% versus 6% transmission attenuated phase shift mask for the 65nm device node
Montgomery, Patrick K.; Litt, Lloyd; Conley, Will; Lucas, Kevin; van Wingerden, Johannes; Vandenberghe, Geert; Wiaux, Vincent (2004) -
Comparisons of 9% versus 6% transmission attenuated phase-shift mask for the 65nm device mode
Montgomery, Patrick K.; Lucas, Kevin D.; Litt, Lloyd C.; Conley, Will; Fanucchi, Eric; van Wingerden, Johannes; Vandenberghe, Geert; Wiaux, Vincent; Taylor, Darren; Cangemi, Michael J.; Kasprowicz, Bryan (2003-12) -
Critical pattern behavior at nanometer scale vicinity of black border
Kovalevich, Tatiana; Bekaert, Joost; Wiaux, Vincent; Liddle, Jack; Davydova, Natalia; Tien, Ming-Chun (2019) -
Deep UV lithography for mass-manufacturing photonic crystal-based components
Bogaerts, Wim; Taillaert, Dirk; Baets, Roel; Wiaux, Vincent; Beckx, Stephan (2002) -
Deep UV lithography for planar photonic crystal structures
Bogaerts, Wim; Dumon, Pieter; Van Campenhout, Joris; Wiaux, Vincent; Wouters, Johan M. D.; Beckx, Stephan; Taillaert, Dirk; Luyssaert, Bert; Van Thourhout, Dries; Baets, Roel (2003-10) -
Density limits in logic metal1 using double patterning
Wiaux, Vincent; Verhaegen, Staf; Fenger, Germain; Wong, Patrick (2009) -
Design split algorithms validation for DPT implementation at 32 nm and beyond
Tritchkov, Alexander; Kempsell, Monica; Glotov, Petr; Sahouria, Emile; Komirenko, Sergiy; Wiaux, Vincent (2008) -
Design split and double exposure for contact hole printing at 0.40 k1 and beyond
Köhler, Carsten; van Praagh, Judith; Finders, Jo; Wiaux, Vincent; Vandenberghe, Geert (2004) -
Detection of split design-related weak points in double patterning using PQW and bright-field defect inspection
Van Den Heuvel, Dieter; Cheng, Shaunee; Leray, Philippe; Wiaux, Vincent; Maenhoudt, Mireille; D'have, Koen; Jaenen, Patrick; Marcuccilli, Gino; Malik, Irfan; Klein, Sophie (2008) -
Double litho, double etch (LELE) process challenges for 22nm HP and beyond
Maenhoudt, Mireille; Wiaux, Vincent; Cheng, Shaunee; Vandenberghe, Geert; Ronse, Kurt (2008) -
Double patterning at NA 0.33 versus high-NA single exposure in EUV lithography: an imaging comparison
Gao, Weimin; Wiaux, Vincent; Hoppe, Wolfgang; Philipsen, Vicky; Melvin, Lawrence; Hendrickx, Eric; Lucas, Kevin; Kim, Ryan Ryoung han (2018) -
Double patterning design split implementation and validation for the 32nm node
Drapeau, Martin; Wiaux, Vincent; Hendrickx, Eric; Verhaegen, Staf; Machida, Takahiro (2007) -
Double patterning EDA solutions for the 32nm HP and beyond
Bailey, George; Tritchkov, Alexander; Park, Jea-Woo; Hong, Le; Wiaux, Vincent; Hendrickx, Eric; Verhaegen, Staf; Xie, Peng; Versluijs, Janko (2007) -
Double patterning induced process bias induced for various LPL alternatives
Wong, Patrick; Vandenbroeck, Nadia; Wiaux, Vincent; Gronheid, Roel (2010) -
Double patterning OPC and design for 22nm to 16nm device nodes
Lucas, Kevin; Cork, Chris; Miloslavsky, Alex; Luk-Pat, Gerry; Li, Xiaohai; Barnes, Levi; Gao, Weimin; Wiaux, Vincent (2009)