Browsing by author "Stucchi, Michele"
Now showing items 41-60 of 139
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Design strategy for integrating DSA via patterning in sub-7 nm interconnects
Karageorgos, Ioannis; Ryckaert, Julien; Tung, C. Maryann; Wong, H.-S. Philip; Gronheid, Roel; Bekaert, Joost; Croes, Kris; Karageorgos, Evangelos; Vandenberghe, Geert; Stucchi, Michele; Dehaene, Wim (2016) -
Design, verification and simulation of 3D circuit
Katti, Guruprasad; De Wachter, Bart; Nelis, Marc; Dehan, Morin; Cupak, Miroslav; Croes, Kris; Beeckman, Gerd; Marchal, Pol; Stucchi, Michele (2009) -
Dielectric reliability of highly scaled through silicon via for wafer level 3D-SoC applications
Li, Yunlong; Van Huylenbroeck, Stefaan; De Vos, Joeri; Wu, Chen; Stucchi, Michele; Croes, Kristof; Van der Plas, Geert; Beyer, Gerald; Beyne, Eric (2018) -
Diffusion barrier integrity and electrical performance of Cu/porous dielectric damascene lines
Iacopi, Francesca; Tokei, Zsolt; Stucchi, Michele; Lanckmans, Filip; Maex, Karen (2003) -
Electrical characterization method to study barrier integrity in 3D through-silicon vias
Li, Yunlong; Velenis, Dimitrios; Kauerauf, Thomas; Stucchi, Michele; Civale, Yann; Redolfi, Augusto; Croes, Kristof (2012) -
Electrical modeling and characterization of through silicon via for three-dimensional ICs
Katti, Guruprasad; Stucchi, Michele; De Meyer, Kristin; Dehaene, Wim (2010) -
Electromigration behavior of 2μm sub-micron Cu/SiCN hybrid bonds
De Messemaeker, Joke; Kim, Soon-Wook; Stucchi, Michele; Beyer, Gerald; Beyne, Eric; Croes, Kristof (2019) -
Electromigration behavior of Cu/SiCN to Cu/SiCN hybrid bonds for 3D integrated circuits
De Messemaeker, Joke; Kim, Soon-Wook; Stucchi, Michele; Beyer, Gerald; Beyne, Eric; Croes, Kristof (2018) -
Enabling 10μm pitch hybrid Cu-Cu IC stacking with Through Silicon Vias
Huyghebaert, Cedric; Van Olmen, Jan; Okoro, Chukwudi; Coenen, Jens; Jourdain, Anne; Van Cauwenberghe, Marc; Agarwal, Rahul; Phommahaxay, Alain; Stucchi, Michele; Soussan, Philippe (2010) -
Enabling interconnect scaling with spacer-defined double patterning (SDDP)
Siew, Yong Kong; Stucchi, Michele; Versluijs, Janko; Roussel, Philippe; Kunnen, Eddy; Pantouvaki, Marianna; Beyer, Gerald; Tokei, Zsolt (2013) -
Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration
Jourdain, Anne; Schleicher, Filip; De Vos, Joeri; Stucchi, Michele; Chery, Emmanuel; Miller, Andy; Beyer, Gerald; Van der Plas, Geert; Walsby, Edward; Roberts, Kerry; Ashraf, Huma; Thomas, Dave; Beyne, Eric (2020) -
Fine grain thermal modelling and expermintal validation of 3D-ICs
Oprins, Herman; Srinivasan, Adi; Cupak, Miroslav; Cherman, Vladimir; Torregiani, Cristina; Stucchi, Michele; Van der Plas, Geert; Marchal, Pol; Vandevelde, Bart; Cheng, Ed (2011-04) -
Frequency dependence in interline capacitance measurements
Stucchi, Michele; Maex, Karen (2002) -
Frequency-dependent line capacitance and conductance calculations of on-chip interconnects on silicon substrate using Fourier cosine series approach
Ymeri, Hasan; Nauwelaers, Bart; Vandenberghe, S.; Maex, Karen; De Roest, David; Stucchi, Michele (2001) -
Highly accurate closed form approximation for frequency-dependent line impedance of a lossy silicon substrate IC interconnect
Ymeri, Hasan; Nauwelaers, Bart; Maex, Karen; De Roest, David; Stucchi, Michele (2002) -
Hot topics in IC and electronic system testing – from all angles
Marinissen, Erik Jan; Gielen, Georges; Stucchi, Michele; V "at "ajelu, Elena-Ioana (2021-05) -
Hydrogen outgassing induced liner barrier reliability degradation in through silicon via's
Li, Yunlong; Oba, Yoshiyuki; Wu, Chen; Van Huylenbroeck, Stefaan; Van Besien, Els; Vereecke, Guy; Stucchi, Michele; De Wolf, Ingrid; Beyer, Gerald; Beyne, Eric; Croes, Kristof (2014) -
Impact of 3D design choices on manufacturing cost
Velenis, Dimitrios; Stucchi, Michele; Marinissen, Erik Jan; Swinnen, Bart; Beyne, Eric (2009) -
Impact of advanced patterning options, 193nm and EUV, on local interconnect performance
Stucchi, Michele; Tokei, Zsolt; Demuynck, Steven; Siew, Yong Kong (2012) -
Impact of backside process on high aspect ratio via-middle Cu through silicon via reliability
Li, Yunlong; Van Huylenbroeck, Stefaan; De Vos, Joeri; Stucchi, Michele; Croes, Kristof; Beyer, Gerald; Beyne, Eric (2017-06)