Recently added

Gate architecture design for enhancement mode p-GaN gate HEMTs for 200 and 650V applications

Posthuma, Niels; You, Shuzhen; Stoffels, Steve; Liang, Hu; Zhao, Ming; Decoutere, Stefaan (2018)

A new method to fabricate Ge nanowires: selective lateral etching of GeSn:P-Ge multi-stacks

Porret, Clément; Vohra, Anurag; Sebaai, Farid; Douhard, Bastien; Hikavyy, Andriy; Loo, Roger (2018)

Ga-doped Ge and [B + Ga] Co-doped SiGe epitaxial source-drain for Sub-7 nm logic devices

Porret, Clément; Margetis, Joe; Tolle, John; Sammak, Amir; Scappucci, Giordano; Petersen Barbosa Lima, Lucas; Kohen, David; Kunert, Bernardette; Hikavyy, Andriy; Loo, Roger (2018)

Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration

Porret, Clément; Hikavyy, Andriy; Gomez Granados, Juan Fernando; Baudot, Sylvain; Vohra, Anurag; Kunert, Bernardette; Douhard, Bastien; Bogdanowicz, Janusz; Schaekers, Marc; Kohen, David; Margetis, Joe; Tolle, John; Petersen Barbosa Lima, Lucas; Sammak, Amir; Scappucci, Giordano; Rosseel, Erik; Langer, Robert; Loo, Roger (2018)

Very low temperature epitaxy of group-IV semiconductors for use in finFET, stacked nanowires and monolithic 3D integration

Porret, Clément; Hikavyy, Andriy; Gomez Granados, Juan Fernando; Baudot, Sylvain; Vohra, Anurag; Kunert, Bernardette; Douhard, Bastien; Bogdanowicz, Janusz; Schaekers, Marc; Kohen, David; Margetis, Joe; Tolle, John; Petersen Lima, Lucas; Sammak, Amir; Scappucci, Giordano; Rosseel, Erik; Langer, Robert; Loo, Roger (2018)

High-performance (EOT<0.4nm, Jg~10-7A/cm2) ALD-deposited Ru\SrTiO3 stack for next generations DRAM pillar capacitor

Popovici, Mihaela Ioana; Belmonte, Attilio; Oh, Hyungrock; Potoms, Goedele; Meersschaut, Johan; Richard, Olivier; Hody, Hubert; Van Elshocht, Sven; Delhougne, Romain; Goux, Ludovic; Kar, Gouri Sankar (2018)

Structured inference networks using high-dimensional sensors for surveillance purposes

Polfliet, Vincent; Knudde, Nicolas; Vandersmissen, Baptist; Couckuyt, Ivo; Dhaene, Tom (2018)

High density and high bandwidth chip-to-chip connections with 20μm pitch flip-chip on fan-out wafer level package

Podpod, Arnita; Velenis, Dimitrios; Phommahaxay, Alain; Bex, Pieter; Fodor, Ferenc; Marinissen, Erik Jan; Rebibis, Kenneth June; Miller, Andy; Beyer, Gerald; Beyne, Eric (2018)

A novel fan-out concept for ultra-high chip-to-chip interconnect density with 20-μm pitch

Podpod, Arnita; Slabbekoorn, John; Phommahaxay, Alain; Duval, Fabrice; Salahouelhadj, Abdellah; Gonzalez, Mario; Rebibis, Kenneth June; Miller, Andy; Beyer, Gerald; Beyne, Eric (2018)

TDoA-based outdoor positioning in a public LoRa network

Podevijn, Nico; Trogh, Jens; Karaagac, Abdulkadir; Haxhibeqiri, Jetmir; Hoebeke, Jeroen; Martens, Luc; Suanet, Pieter; Hendrikse, Kim; Plets, David; Joseph, Wout (2018)

Performance comparison of RSS algorithms for indoor localisation in large open environments

Podevijn, Nico; Plets, David; Trogh, Jens; Karaagac, Abdulkadir; Haxhibeqiri, Jetmir; Hoebeke, Jeroen; Martens, Luc; Suanet, Pieter; Joseph, Wout (2018)

Efail: breaking S/MIME and OpenPGP email encryption using Exfiltration channels

Poddebniak, Damian; Dresen, Christian; Muller, jens; Ising, Fabian; Schinzel, Sebastian; Friedberger, Simon (2018)

Experimental performance evaluation of outdoor TDoA and RSS positioning in a public LoRa network

Plets, David; Podevijn, Nico; Trogh, Jens; Martens, Luc; Joseph, Wout (2018)

Monte-Carlo simulation of the impact of LED power uncertainty on visible light positioning accuracy

Plets, David; Bastiaens, Sander; Stevens, Nobby; Martens, Luc; Joseph, Wout (2018)

O-band energy-efficient broadcast-friendly interconnection scheme with SiPho Mach-Zehnder Modulator (MZM) & Arrayed Waveguide Grating Router (AWGR)

Pitris, Stelios; Mitsolidou, Charoula; Alexoudi, Theoni; Perez-Galacho, Diego; Vivien, Laurent; Baudot, Charles; De Heyn, Peter; Van Campenhout, Joris; Marris-Morini, Delphine; Pleros, Nikos (2018)

Conference contributions: Recent submissions

Gate architecture design for enhancement mode p-GaN gate HEMTs for 200 and 650V applications

A new method to fabricate Ge nanowires: selective lateral etching of GeSn:P-Ge multi-stacks

Ga-doped Ge and [B + Ga] Co-doped SiGe epitaxial source-drain for Sub-7 nm logic devices

Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration

Very low temperature epitaxy of group-IV semiconductors for use in finFET, stacked nanowires and monolithic 3D integration

High-performance (EOT<0.4nm, Jg~10-7A/cm2) ALD-deposited Ru\SrTiO3 stack for next generations DRAM pillar capacitor

Structured inference networks using high-dimensional sensors for surveillance purposes

High density and high bandwidth chip-to-chip connections with 20μm pitch flip-chip on fan-out wafer level package

A novel fan-out concept for ultra-high chip-to-chip interconnect density with 20-μm pitch

TDoA-based outdoor positioning in a public LoRa network

Performance comparison of RSS algorithms for indoor localisation in large open environments

Efail: breaking S/MIME and OpenPGP email encryption using Exfiltration channels

Experimental performance evaluation of outdoor TDoA and RSS positioning in a public LoRa network

Monte-Carlo simulation of the impact of LED power uncertainty on visible light positioning accuracy

O-band energy-efficient broadcast-friendly interconnection scheme with SiPho Mach-Zehnder Modulator (MZM) & Arrayed Waveguide Grating Router (AWGR)

O-band silicon photonics 8×8 Arrayed Waveguide Grating Router (AWGR) for 1.6 Tb/s on-chip routing

Design of a fully balanced ASIC coprocessor implementing complete addition formulas on Weierstrass

Novel EUV mask absorber evaluation in support of next-generation EUV imaging

Wet-chemical etching of ruthenium in acidic Ce4+ solution

Wet-chemical deposition of alternative metals

Conference contributions: Recent submissions

Gate architecture design for enhancement mode p-GaN gate HEMTs for 200 and 650V applications ﻿

A new method to fabricate Ge nanowires: selective lateral etching of GeSn:P-Ge multi-stacks ﻿

Ga-doped Ge and [B + Ga] Co-doped SiGe epitaxial source-drain for Sub-7 nm logic devices ﻿

Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration ﻿

Very low temperature epitaxy of group-IV semiconductors for use in finFET, stacked nanowires and monolithic 3D integration ﻿

High-performance (EOT<0.4nm, Jg~10-7A/cm2) ALD-deposited Ru\SrTiO3 stack for next generations DRAM pillar capacitor ﻿

Structured inference networks using high-dimensional sensors for surveillance purposes ﻿

High density and high bandwidth chip-to-chip connections with 20μm pitch flip-chip on fan-out wafer level package ﻿

A novel fan-out concept for ultra-high chip-to-chip interconnect density with 20-μm pitch ﻿

TDoA-based outdoor positioning in a public LoRa network ﻿

Performance comparison of RSS algorithms for indoor localisation in large open environments ﻿

Efail: breaking S/MIME and OpenPGP email encryption using Exfiltration channels ﻿

Experimental performance evaluation of outdoor TDoA and RSS positioning in a public LoRa network ﻿

Monte-Carlo simulation of the impact of LED power uncertainty on visible light positioning accuracy ﻿

O-band energy-efficient broadcast-friendly interconnection scheme with SiPho Mach-Zehnder Modulator (MZM) & Arrayed Waveguide Grating Router (AWGR) ﻿

O-band silicon photonics 8×8 Arrayed Waveguide Grating Router (AWGR) for 1.6 Tb/s on-chip routing ﻿

Design of a fully balanced ASIC coprocessor implementing complete addition formulas on Weierstrass ﻿

Novel EUV mask absorber evaluation in support of next-generation EUV imaging ﻿

Wet-chemical etching of ruthenium in acidic Ce4+ solution ﻿

Wet-chemical deposition of alternative metals ﻿

Gate architecture design for enhancement mode p-GaN gate HEMTs for 200 and 650V applications

A new method to fabricate Ge nanowires: selective lateral etching of GeSn:P-Ge multi-stacks

Ga-doped Ge and [B + Ga] Co-doped SiGe epitaxial source-drain for Sub-7 nm logic devices

Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration

Very low temperature epitaxy of group-IV semiconductors for use in finFET, stacked nanowires and monolithic 3D integration

High-performance (EOT<0.4nm, Jg~10-7A/cm2) ALD-deposited Ru\SrTiO3 stack for next generations DRAM pillar capacitor

Structured inference networks using high-dimensional sensors for surveillance purposes

High density and high bandwidth chip-to-chip connections with 20μm pitch flip-chip on fan-out wafer level package

A novel fan-out concept for ultra-high chip-to-chip interconnect density with 20-μm pitch

TDoA-based outdoor positioning in a public LoRa network

Performance comparison of RSS algorithms for indoor localisation in large open environments

Efail: breaking S/MIME and OpenPGP email encryption using Exfiltration channels

Experimental performance evaluation of outdoor TDoA and RSS positioning in a public LoRa network

Monte-Carlo simulation of the impact of LED power uncertainty on visible light positioning accuracy

O-band energy-efficient broadcast-friendly interconnection scheme with SiPho Mach-Zehnder Modulator (MZM) & Arrayed Waveguide Grating Router (AWGR)

O-band silicon photonics 8×8 Arrayed Waveguide Grating Router (AWGR) for 1.6 Tb/s on-chip routing

Design of a fully balanced ASIC coprocessor implementing complete addition formulas on Weierstrass

Novel EUV mask absorber evaluation in support of next-generation EUV imaging

Wet-chemical etching of ruthenium in acidic Ce4+ solution

Wet-chemical deposition of alternative metals