Multi-VT Options at Scaled Vertical Pitch in Gate-All-Around Nanosheet Devices by Independent Inner-Outer Work-function Tuning

Abstract

Using an advanced design technology co-optimization (DTCO) framework, we investigate multi-threshold (multi-V-T) options in gate-all-around nanosheet ( GAA-NS) FETs at ultra-scaled vertical pitch. This is achieved by allowing inner-gate work-function to be pinned due to very thin metal layers, while only modulating outer-gate work-function. It is shown, that while inner-outer work-function mismatch does result in on-current degradation, the impact is not significant within the mismatch range required (+/- 300 meV) to achieve 3-V-T device options. Thus, we propose a path for vertical pitch scaling whereby, higher stacked NS can be processed with relative ease in addition to enhanced performance.