High Density 360 /μm Aligned CNT FET with ION>1 mA/μm at -0.5 V VD and 30nm Lch

Abstract

In this work, we demonstrate high performance FETs integrated on high density aligned carbon nanotube (A-CNT) arrays and perform statistical analysis. The back-gate pFETs show I-on>1.2 mA/mu m, R-c similar to 91 ohm center dot mu m, whereas the dual-gate pFETs show I-on similar to 800 mu A/mu m, on-off ratio similar to 5 x10(3) at 30 nm channel length (L-ch) and -0.5 V V-d. The impact of gate dielectric, EOT scaling and post-fabrication annealing on the device performance are explored in batch. With process optimization, the on-state performance of dual-gate A-CNT FETs is approaching silicon technology.