Enabling 0.33NA EUV lithography patterning towards MP16 SADP semi-damascene metallization, setting the benchmark for High-NA EUV

Abstract

To accommodate the A10 node a further scaling down of the metal line pitch towards MP16 is envisaged. As high NA will be close to its practical limit for direct P16 L/S patterning, low NA self-aligned double patterning (SADP) from P32 towards P16 was explored. First, lithography conditions such as source and stack were optimized by investigating process windows, uLER/uLWR and ebeam defectivity throughout the P32 core patterning process. Then, with the optimized lithography conditions a CDU wafer was subjected to SADP patterning.