Browsing by Author "Beyer, Gerald"
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Publication 10 and 7 mu m Pitch Thermo-compression Solder Joint, Using A Novel Solder Pillar And Metal Spacer Process
Proceedings paper2020, 70th IEEE Electronic Components and Technology Conference (ECTC), JUN 03-30, 2020, p.617-622Publication 3D chip package interaction thermo-mechanical challenges: proximity effects of through silicon vias and μ-bumps
Proceedings paper2012, IEEE International Conference on IC Design and technology - ICICDT, 30/05/2012Publication 3D IC assembly using thermal compression bonding and wafer-level underfill – strategies for quality improvement and throughput enhancement
Proceedings paper2016, IEEE 18th Electronic Packaging Technology Conference - EPTC, 30/11/2016, p.791-796Publication 3D integration challenges for fine pitch back side micro-bumping on ZoneBOND™ wafers
Proceedings paper2012, 4th Electronics System Integration Technologies Conference - ESTC, 17/09/2012Publication 3D interconnects for quantum computing
Proceedings paper2024, IEEE 74th Electronic Components and Technology Conference (ECTC), MAY 28-31, 2024, p.821-828Publication 3D SoC integration, beyond 2.5D chiplets
Proceedings paper2021, IEEE International Electron Devices Meeting (IEDM), DEC 11-16, 2021Publication 3D stacking cobalt and nickel microbumps and kinetics of corresponding IMCs at low temperatures
Proceedings paper2017, IEEE International Interconnect Technology Conference - IITC, 16/05/2017, p.1-3Publication 3D stacking induced mechanical stress effects
Proceedings paper2014, IEEE 64th Electronic Components and Technology Conference - ECTC, 27/05/2014, p.309-315Publication 3D stacking of Co and Ni based microbumps
; ; ; ; Publication 3D stacking using bump-less process for sub 10μm pitches
Proceedings paper2016, IEEE 66th Electronic Components and Technology Conference - ECTC, 31/05/2016, p.128-133Publication 3D stacking using Cu-Cu direct bonding
Proceedings paper2012-02, IEEE International 3D System Integration Conference - 3DIC, 31/01/2012, p.1-MarPublication 3D-SoC integration utilizing high accuracy wafer level bonding
Proceedings paper2016, IEEE 18th Electronics Packaging Technology Conference - EPTC, 30/11/2016, p.111-114Publication A feasibility study of dual damascene porous SiLK resin with spin-on hard masks
Proceedings paper2004, Advanced Metallization Conference 2003, 21/10/2003, p.147-151Publication A high-reliable Cu/ULK integration scheme using Metal Hard Mask and Low-k capping film
Oral presentation2007, Advanced Metallization Conference: 17th Asian SessionPublication A highly reliable 1.4μm pitch via-last TSV module for wafer-to-wafer hybrid bonded 3D-SOC systems
Proceedings paper2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 28/05/2019, p.1035-1040Publication A highly reliable 1×5μm via-last TSV module
Proceedings paper2018, IEEE International Interconnect Technology Conference - IITC, 4/06/2018, p.94-96Publication A NEMS based sensor to monitor stress in deep sub-micron Cu/Low-$k$ interconnects
Journal article2009, Semicond. Sci. Technol., (24) 11, p.115018Publication A new perspective of barrier material evaluation and process optimization
Proceedings paper2009, IEEE International Interconnect Technology Conference - IITC, 1/06/2009, p.206-208Publication A novel fan-out concept for ultra-high chip-to-chip interconnect density with 20-μm pitch
Proceedings paper2018, 68th Electronic Components and Technology Conference - ECTC, 29/05/2018, p.370-378