Browsing by Author "Civale, Yann"
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Publication 1.9 nm wide ultra-high aspect-ratio bulk-Si FinFETs
Publication 3D chip package interaction thermo-mechanical challenges: proximity effects of through silicon vias and μ-bumps
Proceedings paper2012, IEEE International Conference on IC Design and technology - ICICDT, 30/05/2012Publication 3D wafer-level packaging die stacking using spin-on-dielectric polymer liner through-silicon vias
Journal article2011, IEEE Transactions on Components, Packaging and Manufacturing Technology, (1) 6, p.833-840Publication Advanced physical analysis of 3D interconnect
Publication Al-mediated solid-phase epitaxy of silicon-on-insulator
Publication Bath stability monitoring for electroless Cu seed formation in high aspect ratio TSV
Meeting abstract2012, ECS Fall Meeting Symposium E8: Processing Materials of 3D Interconnects, 7/10/2012, p.2727Publication Cost comparison between 3D and 2.5D integration
Proceedings paper2012, 4th Electronics System Integration Technologies Conference - ESTC, 17/09/2012, p.1-4Publication Cu electrodeposition for Through-Silicon Via Technology
Meeting abstract2009, 215th Electrochemical Society Spring Meeting, 24/05/2009, p.990Publication Cu to Cu interconnect using 3D-TSV and wafer to wafer thermo-compression bonding
Proceedings paper2010, IEEE International Interconnect Technology Conference - IITC, 6/06/2010Publication Die stacking using 3D-wafer level packaging copper/polymer through-Si via technology and Cu/Sn interconnect bumping
Proceedings paper2009, IEEE International Conference on 3D System Integration, 28/09/2009Publication Dry etch solutions for 3D integration technology
Meeting abstract2010, 3rd Plasma Etch and Strip in Microelectronics Workshop - PESM, 4/03/2010Publication Effect of TSV presence on FEOL yield and reliability
Proceedings paper2013, IEEE International Reliability Physics Symposium - IRPS, 14/04/2013, p.5C.6Publication Electrical characterization method to study barrier integrity in 3D through-silicon vias
Proceedings paper2012, 62nd Electronic Components and Technology Conference - ECTC, 29/05/2012Publication Electrodeposition for 3D integration
Proceedings paper2010, Symposium " Galvanik " Eine etablierte Technik innovativ angewendet, 25/11/2010, p.31-36Publication Electroless copper bath stability monitoring with UV-VIS spectroscopy, pH, and mixed potential measurements
Journal article2012, Journal of the Electrochemical Society, (159) 7, p.D437-D441Publication Electroless Cu deposition on atomic layer deposited Ru as novel seed formation process in through-Si vias
Journal article2013, Electrochimica Acta, 100, p.203-211Publication Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-Silicon Via Interconnects
Proceedings paper2012, 62th Electronic Components and Technology Conference - ECTC, 29/05/2012Publication ESH friendly solvent for stripping positive and negative photoresists in 3D-wafer level packaging and 3D-stacked IC applications
Journal article2012, Solid State Phenomena, 187, p.223-226Publication ESH solvent for stripping positive and negative photoresists in 3D-WLP and 3D-SIC applications
Meeting abstract2010, 10th International Symposium on Ultra-Clean Processing of Semiconductor Devices - UCPSS, 19/09/2010, p.58-59Publication Fabrication and electrical evaluation of va last polymer liner TSVs
Journal article2010, Journal of Microelectronics and Electronic Packaging, (7) 3, p.125-130
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