Browsing by Author "Gravey, Virginie"
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Publication Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
Journal article2012, Solid-State Electronics, 71, p.106-112Publication Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
Proceedings paper2011-03, 12th International Conference on Ultimate Integration on Silicon - ULIS, 14/03/2011, p.31-33Publication Demonstration of scaled 0.099μm² FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology
Proceedings paper2009-12, IEEE International Electron Devices Meeting - IEDM, 7/12/2009, p.301-304Publication Implementation of Ru based barriers in 50 nm half pitch single damascene Cu/SiCOH (k=2.5) structures
; ; ; ; Proceedings paper2009, Advanced Metallization Conference 2008 (AMC2008), 23/09/2008, p.91-97Publication Implementation of Ru based barriers in 50 nm half pitch single damascene Cu/SiCOH (k=2.5) structures
; ; ; ; Meeting abstract2008, Advanced Metallization Conference - AMC, 23/09/2008Publication Integration of 20nm half pitch single damascene copper trenches by spacer-defined double patterning (SDDP) on metal hard mask (MHM)
; ; ; ; Proceedings paper2010, IEEE International Interconnect Technology Conference - IITC, 7/06/2010Publication Metallization of sub- 30 nm Interconnects: Comparison of different liner/seed combinations
Proceedings paper2009, Proceedings of the IEEE International Interconnect Technology Conference, 1/06/2009, p.200-202Publication On the thermal stability of physically-vapor-deposited diffusion barriers in 3D through-silicon vias during IC processing
Journal article2013, Microelectronic Engineering, 106, p.155-159Publication Plasma enhanced atomic layer deposition of ruthenium ultra-thin films for advanced metallization
Meeting abstract2010, AVS 57th International Symposium & Exhibition, 17/10/2010Publication Scalability of plasma enhanced atomic layer deposited ruthenium films for interconnect applications
Journal article2012, Journal of Vacuum Science and Technology A, (30) 1, p.01A103Publication Spacer defined double patterning for 20nm half pitch interconnect damascene structures
; ; ; ; Publication Thermal stability of copper through-silicon via barriers during IC processing
Proceedings paper2011, IEEE International Interconnect Technology Conference and Materials for Advanced Metallization - IITC/MAM, 8/05/2012, p.P2.51