Browsing by Author "Guo, Wei"

3D chip package interaction thermo-mechanical challenges: proximity effects of through silicon vias and μ-bumps

3D stacking induced mechanical stress effects

Analysis of copper plasticity impact in TSV-middle and backside TSV-last fabrication processes

Anodic electrodeposition of continuous metal-organic framework films with robust adhesion by pre-anchored strategy

Chip package interaction: A stress analysis on 3D IC's packages

Chip-package interaction

Chip-package interaction in 3D stacked IC packages using finite element modelling

Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology

Cu TSV stress: avoiding Cu protrusion and impact on devices

IC-package interaction

Impact of 3D integration on 7nm high mobility channel devices operating in the ballistic regime

Impact of strain and source/drain engineering on the low-frequency noise behaviour in n-channel Tri-Gate FinFETs

Impact of through silicon via induced mechanical stress on fully depleted bulk FinFET technology

Impact of wafer thinning on front-end reliability for 3D integration

Low-frequency noise assessment of silicon passivated Ge pMOSFETs with TiN/TaN/HfO2 gate stack

Modeling copper plastic deformation and liner viscoelastic flow effects on performance and reliability in Through Silicon Via (TSV) fabrication processes

Noise coupling between TSVs and active devices: planar nMOSFETs vs. nFinFETs

Performance and reliability impact of copper plasticity in backside TSV-last fabrication process

Reliability challenges related to TSV integration and 3D stacking

Study of 3D process impact on advanced CMOS devices