Browsing by Author "Higuchi, Yuichi"

Effective work function engineering for aggressively scaled planar and FinFET-based devices with high-k last replacement metal gate technology

Effective work function engineering for aggressively scaled planar and multi-gate fin field-effect transistor-based devices with high-k last replacement metal gate technology

Gate-last vs. gate-first technology for aggressively scaled EOT Logic/RF CMOS

Highly scalable effective work function engineering approach for multi-VT modulation of planar and FinFET-based RMG high-k last devies for (sub-)22nm nodes

Implementing cubic-phase HfO2 with $j-value ~ 30 in low-VT replacementgate pMOS devices for improved EOT-Scaling and reliability

Negative Bias Temperature Instability (NBTI) in p-FinFETs with 45-degree substrate rotation

On the oxide trap density and profiles of 1-nm EOT metal-gate last CMOS transistors assessed by low-frequency noise

Process control & integration options of RMG Technology for aggressively scaled devices

Thermal and SF6-plasma treatments for improved (sub-)1nm EOT planar and FinFET-based RMG high-k last devices and enabling a simplified scalable CMOS integration scheme

W versus Co–Al as gate fill-metal for aggressively scaled replacement high-k/metal gate devices for (Sub-)22nm technology nodes

W vs. Co-Al as gate fill-metal for aggressively scaled replacement high-k/metal gate devices for (Sub-)22nm technology nodes