Browsing by Author "Hoffmann, Thomas Y."
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Publication 1mA/μm-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D
; ; ; ; Proceedings paper2011, Symposium on VLSI Technology, 13/06/2011, p.134-135Publication 3D stacked IC demonstration using a through silicon via first approach
Proceedings paper2008, Technical Digest International Electron Devices Meeting - IEDM, 15/12/2008, p.603-606Publication 6Å EOT Si0.45Ge0.55 pMOSFET with optimized reliability (VDD=1V): Meeting the NBTI lifetime target at ultra-thin EOT
Proceedings paper2010, IEEE International Electron Devices Meeting - IEDM, 6/12/2010, p.70-73Publication 8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS
Proceedings paper2010, IEEE Symposium on VLSI Technology, 15/06/2010, p.181-182Publication A 50nm high-k poly silicon gate stack with a buried SiGe channel
Proceedings paper2007, International Symposium on VLSI Technology, Systems and Applications, 23/04/2007Publication A fast and accurate method to study the impact of interface traps on germanium MOS performance
Journal article2011, IEEE Transactions on Electron Devices, (58) 4, p.938-944Publication Advanced 2D/3D simulations for laser annealed device using an atomic kinetic monte carlo approach and scanning spreading resistance microscopy (SRRM)
Proceedings paper2008, Technical Digest International Electron Devices Meeting - IEDM, 15/12/2008, p.539-542Publication Advanced FinFET devices for sub-32nm technology nodes: characteristics and integration challenges
Proceedings paper2009, Silicon-on-Insulator Technology and Devices 14, 24/05/2009, p.45-54Publication Advanced PBTI reliability with 0.69nm EOT GdHfO gate dielectric
Journal article2011, Solid-State Electronics, (63) 1, p.5-7Publication Advanced USJ for high-k / metal gate CMOS devices
Meeting abstract2008, MRS Spring Meeting Symposium E: Doping Engineering for Front-End Processing, 24/03/2008, p.E4.7Publication Advancing CMOS beyond the Si roadmap with Ge and III/V devices
; ; ; ; Publication An analytical compact model for estimation of stress in multiple through-silicon via configurations
Proceedings paper2011, Design, Automation and Test in Europe Conference - DATE, 14/03/2011, p.505-506Publication Analysis of As, P diffusion and defect evolution during sub-millisecond non-melt laser annealing based on an atomistic kinetic Monte Carlo approach
Proceedings paper2007, Technical Digest International Electron Devices Meeting - IEDM, 10/12/2007, p.955-958Publication Analysis of pocket profile deactivation and its impact on Vth variation for laser annealed device using an atomistic kinetic Monte Carlo approach
Proceedings paper2010, IEEE International Electron Devices Meeting - IEDM, 6/12/2010, p.383-386Publication Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession
Journal article2010, Solid-State Electronics, (54) 9, p.855-860Publication Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
Journal article2012, Solid-State Electronics, 71, p.106-112Publication Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
Proceedings paper2011-03, 12th International Conference on Ultimate Integration on Silicon - ULIS, 14/03/2011, p.31-33Publication Buried silicon-germanium pMOSFETs: experimental analysis in VLSI logic circuits under aggressive voltage scaling
Journal article2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (20) 8, p.1487-1495Publication Carbon-based thermal stabilization techniques for junction and silicide engineering for high performance CMOS periphery in memory applications
Proceedings paper2009, 10th International Conference on Ultimate Integration of Silicon - ULIS, 18/03/2009, p.147-150