Browsing by author "Vandevelde, Bart"
Now showing items 1-20 of 281
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3D chip package interaction thermo-mechanical challenges: proximity effects of through silicon vias and μ-bumps
Guo, Wei; Van der Plas, Geert; Ivankovic, Andrej; Eneman, Geert; Cherman, Vladimir; De Wachter, Bart; Mercha, Abdelkarim; Gonzalez, Mario; Civale, Yann; Redolfi, Augusto; Buisson, Thibault; Jourdain, Anne; Vandevelde, Bart; Rebibis, Kenneth June; De Wolf, Ingrid; La Manna, Antonio; Beyer, Gerald; Beyne, Eric; Swinnen, Bart (2012) -
3D technology roadmap and status
Marchal, Pol; Van der Plas, Geert; Eneman, Geert; Moroz, V.; Badaroglu, Mustafa; Mercha, Abdelkarim; Thijs, Steven; Linten, Dimitri; Katti, Guruprasad; Stucchi, Michele; Vandevelde, Bart; Oprins, Herman; Cherman, Vladimir; Croes, Kris; Redolfi, Augusto; La Manna, Antonio; Travaly, Youssef; Beyne, Eric; Cartuyvels, Rudi (2011) -
3D thermal modeling for a photovoltaic module
Chatterjee, Urmimala; Catthoor, Francky; Appels, Reinhart; Oprins, Herman; Van Wichelen, Koen; Vandevelde, Bart; Driesen, Johan; Baert, Kris (2011) -
A finite element study of process induced stress in the transistor channel: effects of silicide contact and gate stack
Torregiani, Cristina; Liu, Joy; Vandevelde, Bart; Degryse, Dominiek; Van Dal, Mark; Benedetti, Alessandro; Lauwers, Anne; Maex, Karen (2004) -
A generic methodology for deriving compact dynamic thermal models, applied to the PSGA package
Christiaens, Filip; Vandevelde, Bart; Beyne, Eric; Mertens, Robert; Bergmans, J. (1998) -
A Hybrid Model for Prognostic and Health Management of Electronic Devices
Murgia, Alessandro; Harsha, Chaitra; Tsiporkova, Elena; Nawghane, Chinmay; Vandevelde, Bart (2024) -
A multilevel sub-modeling approach to evaluate 3D IC packaging induced stress on hybrid interconnect structures
Lofrano, Melina; Gonzalez, Mario; Vandevelde, Bart (2014) -
A multilevel sub-modeling approach to evaluate 3D IC packaging induced stress on hybrid interconnect structures
Lofrano, Melina; Gonzalez, Mario; Vandevelde, Bart; Tokei, Zsolt (2013) -
A novel generic gateway protection configuration applied to ATM networks
Struyve, Kris; Vandevelde, Bart; Demeester, Piet (1997) -
A novel interworking configuration to protect gateways in between survivable subnetworks
Struyve, Kris; Vandevelde, Bart; Demeester, Piet (1997) -
A novel mechanism of embrittlement affecting the impact reliability of tin-based lead-free solder joints
Lambrinou, Konstantza; Maurissen, Wout; Limaye, Paresh; Vandevelde, Bart; Verlinden, Bert; De Wolf, Ingrid (2009) -
A Novel Pin-fin Based Cooling Device for Autonomous Driving High-performance Computers
Nazemi, S. Majid; Pappaterra, Antonio; Verleysen, Willem; Vandevelde, Bart; Neugebauer, Fabian; Janssens, Michel (2021) -
A PoF based methodology to assess the reliability of a sensor module operating in harsh industrial environments
Nawghane, Chinmay; Vandevelde, Bart; Labie, Riet; Michiels, Sam; Hughes, Danny; Liu, Mengyao (2022-04-20) -
A practical approach to thermal modeling and validation of 3D-ICs
Cupak, Miroslav; Oprins, Herman; Van der Plas, Geert; Marchal, Pol; Vandevelde, Bart; Srinivasan, Adi; Cheng, Edmund (2010) -
A study of brittle to ductile fracture transition temperatures in bulk Pb-free solders
Ratchev, Petar; Loccufier, Tony; Vandevelde, Bart; Verlinden, Bert; Teliszewski, Steven; Werkhoven, Daniel; Allaert, Bart (2005) -
Advanced (Metal 3D-Printed) Direct Liquid Jet-Impingement Cooling Solution for Autonomous Driving High-Performance Vehicle Computer (HPVC)
Pappaterra, Antonio; Vandevelde, Bart; Nazemi, Majid; Verleysen, Willem; Oprins, Herman (2021) -
An analysis of the reliability of a wafer level package (WLP) using a silicon under the bump (SUB) configuration
Gonzalez, Mario; Vandevelde, Bart; Vanden Bulcke, Mathieu; Winters, Christophe; Beyne, Eric; Lee, Y.J.; Harkness, B.R.; Mohamed, M.; Meynen, H.; Vanlathem, E. (2003) -
An integrated creep, crack growth and thermo-mechanical fatigue model for WLCSP assemblies soldered with SAC 405
Limaye, Paresh; Vandevelde, Bart; Vandepitte, Dirk; Verlinden, Bert (2009) -
Analysis of microbump induced stress effects in 3D stacked IC technologies
Ivankovic, Andrej; Van der Plas, Geert; Moroz, V.; Choi, M.; Cherman, Vladimir; Mercha, Abdelkarim; Marchal, Pol; Gonzalez, Mario; Eneman, Geert; Zhang, Wenqi; Buisson, Thibault; Detalle, Mikael; La Manna, Antonio; Verkest, Diederik; Beyer, Gerald; Beyne, Eric; Vandevelde, Bart; De Wolf, Ingrid; Vandepitte, Dirk (2012) -
Analysis of the induced stresses in silicon during thermocompression Cu-Cu bonding of Cu-through-vias in 3D-SIC architecture
Okoro, Chukwudi; Eneman, Geert; Gonzalez, Mario; Vandevelde, Bart; Swinnen, Bart; Stoukatch, Serguei; Beyne, Eric; Vandepitte, Dirk (2007-05)