Browsing by author "Collaert, Nadine"
Now showing items 1-20 of 694
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1.5×10-9 Ω·cm² Contact Resistivity on Highly Doped Si:P Using Ge Pre-amorphization and Ti Silicidation
Yu, Hao; Schaekers, Marc; Rosseel, Erik; Peter, Antony; Lee, Joon-Gon; Song, Woo-Bin; Demuynck, Steven; Chiarella, Thomas; Ragnarsson, Lars-Ake; Kubicek, Stefan; Everaert, Jean-Luc; Horiguchi, Naoto; Barla, Kathy; Kim, Daeyong; Collaert, Nadine; Thean, Aaron; De Meyer, Kristin (2015) -
15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process
Mitard, Jerome; Witters, Liesbeth; Loo, Roger; Lee, Seung Hun; Sun, J.W.; Franco, Jacopo; Ragnarsson, Lars-Ake; Brand, A.; Lu, X.; Yoshido, N.; Eneman, Geert; Brunco, David; Vorderwestner, M.; Storck, P.; Milenin, Alexey; Hikavyy, Andriy; Waldron, Niamh; Favia, Paola; Vanhaeren, Danielle; Vanderheyden, Annelies; Richard, Olivier; Mertens, Hans; Arimura, Hiroaki; Sioncke, Sonja; Vrancken, Christa; Bender, Hugo; Eyben, Pierre; Barla, Kathy; Lee, Sun Ghil; Horiguchi, Naoto; Collaert, Nadine; Thean, Aaron (2014) -
25% drive current improvement for p-type Multiple Gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions
Verheyen, Peter; Collaert, Nadine; Rooyackers, Rita; Loo, Roger; Shamiryan, Denis; De Keersgieter, An; Eneman, Geert; Leys, Frederik; Dixit, Abhisek; Goodwin, Michael; Yim, Yong Sik; Caymax, Matty; De Meyer, Kristin; Absil, Philippe; Jurczak, Gosia; Biesemans, Serge (2005) -
3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters
Vandooren, Anne; Wu, Zhicheng; Parihar, Narendra; Franco, Jacopo; Parvais, Bertrand; Matagne, Philippe; Debruyn, Haroen; Mannaert, Geert; Devriendt, Katia; Teugels, Lieve; Vecchio, Emma; Radisic, Dunja; Rosseel, Erik; Hikavyy, Andriy; Chan, BT; Waldron, Niamh; Mitard, Jerome; Besnard, G.; Alvarez, A.; Gaudin, G.; Schwarzenbach, W.; Radu, I.; Nguyen, B. Y.; Huet, K.; Tabata, T.; Mazzamuto, F.; Demuynck, Steven; Boemmels, Juergen; Collaert, Nadine; Horiguchi, Naoto (2020) -
3D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability
Vandooren, Anne; Franco, Jacopo; Parvais, Bertrand; Wu, Zhicheng; Witters, Liesbeth; Walke, Amey; Li, Waikin; Peng, Lan; Deshpande, Veeresh Vidyadhar; Bufler, Fabian; Rassoul, Nouredine; Hellings, Geert; Jamieson, Geraldine; Inoue, Fumihiro; Verbinnen, Greet; Devriendt, Katia; Teugels, Lieve; Heylen, Nancy; Vecchio, Emma; Tao, Zheng; Rosseel, Erik; Vanherle, Wendy; Hikavyy, Andriy; Chan, BT; Ritzenthaler, Romain; Besnard, Guillaume; Schwarzenbach, Walter; Gaudin, Gweltaz; Radu, Ionut; Nguyen, Bich-Yen; Waldron, Niamh; De Heyn, Vincent; Mocuta, Dan; Collaert, Nadine (2018-11) -
3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability
Vandooren, Anne; Franco, Jacopo; Parvais, Bertrand; Wu, Zhicheng; Witters, Liesbeth; Walke, Amey; Li, Waikin; Peng, Lan; Deshpande, Veeresh Vidyadhar; Bufler, Fabian; Rassoul, Nouredine; Hellings, Geert; Jamieson, Geraldine; Inoue, Fumihiro; Verbinnen, Greet; Devriendt, Katia; Teugels, Lieve; Heylen, Nancy; Vecchio, Emma; Tao, Zheng; Rosseel, Erik; Vanherle, Wendy; Hikavyy, Andriy; Chan, BT; Ritzenthaler, Romain; Besnard, Guillaume; Schwarzenbach, Walter; Gaudin, Gweltaz; Radu, Ionut; Nguyen, Bich-Yen; Waldron, Niamh; De Heyn, Vincent; Mocuta, Dan; Collaert, Nadine (2018) -
3D technologies for analog/RF applications
Vandooren, Anne; Parvais, Bertrand; Witters, Liesbeth; Walke, Amey; Vais, Abhitosh; Merckling, Clement; Lin, Dennis; Waldron, Niamh; Wambacq, Piet; Mocuta, Dan; Collaert, Nadine (2017) -
50 nm high performance strained Si/SiGe pMOS devices with multiple quantum wells
Collaert, Nadine; Verheyen, Peter; De Meyer, Kristin; Loo, Roger; Caymax, Matty (2002) -
A 0.314mm2 6T-SRAM cell built with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography
Nackaerts, Axel; Ercken, Monique; Demuynck, Steven; Lauwers, Anne; Baerts, Christina; Bender, Hugo; Boullart, Werner; Collaert, Nadine; Degroote, Bart; Delvaux, Christie; de Marneffe, Jean-Francois; Dixit, Abhisek; De Meyer, Kristin; Hendrickx, Eric; Heylen, Nancy; Jaenen, Patrick; Laidler, David; Locorotondo, Sabrina; Maenhoudt, Mireille; Moelants, Myriam; Pollentier, Ivan; Ronse, Kurt; Rooyackers, Rita; Van Aelst, Joke; Vandenberghe, Geert; Vandervorst, Wilfried; Vandeweyer, Tom; Vanhaelemeersch, Serge; Van Hove, Marleen; Van Olmen, Jan; Verhaegen, Staf; Versluijs, Janko; Vrancken, Christa; Wiaux, Vincent; Jurczak, Gosia; Biesemans, Serge (2004-12) -
A 10-bit current-steering FinFET D/A converter
Fulde, Michael; Kuttner, F.; von Armin, Klaus; Parvais, Bertrand; Mercha, Abdelkarim; Collaert, Nadine; Rooyackers, Rita; Becherer, M.; Schmitt-Landsiedel, D.; Knoblinger, G. (2008) -
A 120-140-GHz LNA in 250-nm InP HBT
Chauhan, Vikas; Collaert, Nadine; Wambacq, Piet (2022-07-18) -
A 2nd generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs
Mitard, Jerome; Witters, Liesbeth; Sasaki, Yuichiro; Arimura, Hiroaki; Schulze, Andreas; Loo, Roger; Ragnarsson, Lars-Ake; Hikavyy, Andriy; Cott, Daire; Chiarella, Thomas; Kubicek, Stefan; Mertens, Hans; Ritzenthaler, Romain; Vrancken, Christa; Favia, Paola; Bender, Hugo; Horiguchi, Naoto; Barla, Kathy; Mocuta, Dan; Mocuta, Anda; Collaert, Nadine; Thean, Aaron (2016-06) -
A 50 nm vertical Si0.70/Ge0.30/Si0.85/Ge0.15 pMOSFET with an oxide/nitride gate dielectric
Verheyen, Peter; Collaert, Nadine; Caymax, Matty; Loo, Roger; Van Rossum, Marc; De Meyer, Kristin (2001) -
A 70nm vertical Si/Si1-xGex heterojunction pMOSFET with reduced DIBL sensitivity for VLSI applications
Verheyen, Peter; Collaert, Nadine; Caymax, Matty; Loo, Roger; De Meyer, Kristin; Van Rossum, Marc (1999) -
A defect characterization technique for the sidewall surface of Nano-ridge and Nanowire based Logic and RF technologies
Hsu, B.; Syshchyk, O.; Vais, Abhitosh; Yu, Hao; Alian, AliReza; Mols, Yves; Vondkar Kodandarama, Komal; Kunert, Bernardette; Waldron, Niamh; Simoen, Eddy; Collaert, Nadine (2021) -
A disorder-controlled-kinetics model for Negative Bias Temperature Instability and its experimental verification
Kaczer, Ben; Arkhipov, Vladimir; Degraeve, Robin; Collaert, Nadine; Groeseneken, Guido; Goodwin, Michael (2005-04) -
A functional 41-stage ring oscillator using scaled FinFET devices with 25nm gate lengths and 10nm Fin widths applicable for the 45nm CMOS node
Collaert, Nadine; Dixit, Abhisek; Goodwin, Michael; Kottantharayil, Anil; Rooyackers, Rita; Degroote, Bart; Leunissen, Peter; Veloso, Anabela; Jonckheere, Rik; De Meyer, Kristin; Jurczak, Gosia; Biesemans, Serge (2004-08) -
A low-power HKMG CMOS platform compatible with DRAM node 2x and beyond
Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; Caillat, Christian; Aoulaiche, Marc; Cho, Moon Ju; Noh, Kyung Bong; Son, Yunik; Na, Hoon Jo; Kauerauf, Thomas; Douhard, Bastien; Nazir, Aftab; Chew, Soon Aik; Milenin, Alexey; Altamirano Sanchez, Efrain; Schoofs, Geert; Albert, Johan; Sebaai, Farid; Vecchio, Emma; Paraschiv, Vasile; Vandervorst, Wilfried; Lee, Sun Ghil; Collaert, Nadine; Fazan, Pierre; Horiguchi, Naoto; Thean, Aaron (2014) -
A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM
von Arnim, Klaus; Augendre, Emmanuel; Pacha, C.; Schulz, Thomas; San, Kemal Tamer; Bauer, F.; Nackaerts, Axel; Rooyackers, Rita; Vandeweyer, Tom; Degroote, Bart; Collaert, Nadine; Dixit, Abhisek; Singanamalla, Raghunath; Xiong, W.; Marshall, A.; Cleavelin, C.R.; Schrüfer, K.; Jurczak, Gosia (2007) -
A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C
Collaert, Nadine; Aoulaiche, Marc; De Wachter, Bart; Rakowski, Michal; Redolfi, Augusto; Brus, Stephan; De Keersgieter, An; Horiguchi, Naoto; Altimime, Laith; Jurczak, Gosia (2010)