Browsing by imec author "8e9ef9de79e3f604798a9500160acd478bdb76dd"
Now showing items 1-20 of 44
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5nm: has the time for a device change come?
Raghavan, Praveen; Garcia Bardon, Marie; Schuddinck, Pieter; Jang, Doyoung; Yakimets, Dmitry; Baert, Rogier; Debacker, Peter; Verkest, Diederik; Thean, Aaron (2016) -
A comprehensive benchmark and optimization of 5-nm lateral and vertical GAA 6T-SRAMs
Huynh Bao, Trong; Sakhare, Sushil; Yakimets, Dmitry; Ryckaert, Julien; Thean, Aaron; Mercha, Abdelkarim; Verkest, Diederik; Wambacq, Piet (2016) -
Benchmarking of MoS2 FETs with multigate Si-FET options for 5 nm and beyond
Agarwal Kumar, Tarun; Yakimets, Dmitry; Raghavan, Praveen; Radu, Iuliana; Thean, Aaron; Heyns, Marc; Dehaene, Wim (2015) -
Built-in sheet charge as an alternative to dopant pockets in tunnel field-effect transistors
Verreck, Devin; Verhulst, Anne; Xiang, Yang; Yakimets, Dmitry; El Kazzi, Salim; Parvais, Bertrand; Groeseneken, Guido; Collaert, Nadine; Mocuta, Anda (2018) -
Buried power rail integration with FinFETs for ultimate CMOS scaling
Gupta, Anshul; Varela Pedreira, Olalla; Arutchelvan, Goutham; Zahedmanesh, Houman; Devriendt, Katia; Hanssen, Frederik; Tao, Zheng; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, Noemie; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min-Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Cousserier, Joris; Yakimets, Dmitry; Lazzarino, Frederic; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Jaysankar, Manoj; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Boemmels, Juergen; Demuynck, Steven; Tokei, Zsolt; Horiguchi, Naoto (2020) -
Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
Gupta, Anshul; Mertens, Hans; Tao, Zheng; Demuynck, Steven; Boemmels, Juergen; Arutchelvan, Goutham; Devriendt, Katia; Varela Pedreira, Olalla; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Zahedmanesh, Houman; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, N.; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Yakimets, Dmitry; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frederic; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Tokei, Zsolt; Horiguchi, Naoto (2020) -
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies
Huynh Bao, Trong; Yakimets, Dmitry; Ryckaert, Julien; Ciofi, Ivan; Baert, Rogier; Veloso, Anabela; Boemmels, Juergen; Collaert, Nadine; Roussel, Philippe; Demuynck, Steven; Raghavan, Praveen; Mercha, Abdelkarim; Tokei, Zsolt; Verkest, Diederik; Thean, Aaron; Wambacq, Piet (2014-09) -
Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM
Huynh Bao, Trong; Sakhare, Sushil; Ryckaert, Julien; Yakimets, Dmitry; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron; Wambacq, Piet (2015) -
Device challenges for logic scaling for sub-5 nm node
Jang, Doyoung; Garcia Bardon, Marie; Yakimets, Dmitry; Schuddinck, Pieter; Ragnarsson, Lars-Ake; Sharan, Neha; Parvais, Bertrand; Spessot, Alessio; Verkest, Diederik; Mocuta, Anda (2018) -
Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7
Gupta, Mohit; Weckx, Pieter; Cosemans, Stefan; Schuddinck, Pieter; Baert, Rogier; Yakimets, Dmitry; Jang, Doyoung; Sherazi, Yasser; Raghavan, Praveen; Spessot, Alessio; Mocuta, Anda; Dehaene, Wim (2017) -
Device exploration of nanosheet transistors for sub-7nm technology node
Jang, Doyoung; Yakimets, Dmitry; Eneman, Geert; Schuddinck, Pieter; Garcia Bardon, Marie; Raghavan, Praveen; Spessot, Alessio; Verkest, Diederik; Mocuta, Anda (2017) -
Device-, circuit- & block-level evaluation of CFET in a 4 track library
Schuddinck, Pieter; Zografos, Odysseas; Weckx, Pieter; Matagne, Philippe; Sarkar, Satadru; Sherazi, Yasser; Baert, Rogier; Jang, Doyoung; Yakimets, Dmitry; Gupta, Anshul; Parvais, Bertrand; Ryckaert, Julien; Verkest, Diederik; Mocuta, Anda (2019) -
Device/system performance modeling of stacked lateral NWFET logic
Huang, Victor; Pang, Chenyun; Yakimets, Dmitry; Raghavan, Praveen; Naaemi, Azad (2016) -
Dimensioning for power and performance under 10nm: The limits of FinFETs scaling
Garcia Bardon, Marie; Schuddinck, Pieter; Raghavan, Praveen; Jang, Doyoung; Yakimets, Dmitry; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron (2015) -
DTCO flow for device exploration
Yakimets, Dmitry; Schuddinck, Pieter; Matagne, Philippe; Parvais, Bertrand; Mocuta, Anda (2018) -
Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node
Sakhare, Sushil; Perumkunnil, Manu; Huynh Bao, Trong; Rao, Siddharth; Kim, Woojin; Crotti, Davide; Yasin, Farrukh; Couet, Sebastien; Swerts, Johan; Kundu, Shreya; Yakimets, Dmitry; Baert, Rogier; Oh, Hyungrock; Spessot, Alessio; Mocuta, Anda; Kar, Gouri Sankar; Furnemont, Arnaud (2018) -
Extreme scaling enabled by 5 tracks cells : holistic design-device co-optimization for FinFETs and lateral nanowires
Garcia Bardon, Marie; Sherazi, Yasser; Schuddinck, Pieter; Jang, Doyoung; Yakimets, Dmitry; Debacker, Peter; Baert, Rogier; Mertens, Hans; Badaroglu, Mustafa; Mocuta, Anda; Horiguchi, Naoto; Mocuta, Dan; Raghavan, Praveen; Ryckaert, Julien; Verkest, Diederik; Steegen, An (2016) -
Ge Devices: a potential candidate for sub-5nm nodes?
Sharan, Neha; Shaik, Khaja Ahmad; Jang, Doyoung; Schuddinck, Pieter; Yakimets, Dmitry; Garcia Bardon, Marie; Mitard, Jerome; Arimura, Hiroaki; Bufler, Fabian; Eneman, Geert; Collaert, Nadine; Parvais, Bertrand; Spessot, Alessio; Mocuta, Anda (2019) -
Heterogeneous nano- to wide-scale co-integration of beyond-Si and Si CMOS devices to enhance future electronics
Thean, Aaron; Collaert, Nadine; Radu, Iuliana; Waldron, Niamh; Merckling, Clement; Witters, Liesbeth; Loo, Roger; Mitard, Jerome; Rooyackers, Rita; Vandooren, Anne; Verhulst, Anne; Veloso, Anabela; Yakimets, Dmitry; Huynh Bao, Trong; Chiappe, Daniele; Vaysset, Adrien; Zografos, Odysseas; Caymax, Matty; Huyghebaert, Cedric; Barla, Kathy; Steegen, An (2015) -
Heterogeneous nano-electronic devices enabled by monolithic integration of IIIV, Ge, and Si to expand future CMOS functionality
Thean, Aaron; Collaert, Nadine; Waldron, Niamh; Merckling, Clement; Witters, Liesbeth; Loo, Roger; Mitard, Jerome; Rooyackers, Rita; Vandooren, Anne; Verhulst, Anne; Veloso, Anabela; Pourghaderi, Mohammad Ali; Eneman, Geert; Yakimets, Dmitry; Huynh Bao, Trong; Garcia Bardon, Marie; Ryckaert, Julien; Dehan, Morin; Wambacq, Piet; Caymax, Matty (2014)