Browsing by author "Jansen, Philippe"
Now showing items 1-20 of 39
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0.13µm CMOS technology with optimized poly-Si / NO-oxide gate stack
Kubicek, Stefan; Jansen, Philippe; Badenes, Gonçal; Schaekers, Marc; Kol'dyaev, Victor; Deferm, Ludo; De Meyer, Kristin; Kerr, Daniel; Naem, Abdalla (1999) -
A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits
Vassilev, Vesselin; Vaschenko, Vladislav; Jansen, Philippe; Choi, B.-J.; Concannon, An; Yang, J.-J,; Groeseneken, Guido; Mahadeva Iyer, Natarajan; Terbeek, Marcel; Hopper, Peter; Steyaert, Michiel; Maes, Herman (2004) -
Advanced modeling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies
Vassilev, Vesselin; Lorenzini, Martino; Jansen, Philippe; Groeseneken, Guido; Thijs, Steven; Mahadeva Iyer, Natarajan; Steyaert, M.; Maes, Herman (2004) -
Analysis of high voltage ESD protection devices under HBM ESD stress
Linten, Dimitri; Vashchenko, Vlad; Scholz, Mirko; Jansen, Philippe; Lafonteese, David; Thijs, Steven; Sawada,; Hasebe,; Hopper, Peter; Groeseneken, Guido (2008-05) -
Bonding techniques for single crystal TFT AMLCD's
van der Groen, Sonja; Rosmeulen, Maarten; Jansen, Philippe; Deferm, Ludo; Baert, Kris (1996) -
CMOS compatible wafer scale adhesive bonding for circuit transfer
van der Groen, Sonja; Rosmeulen, Maarten; Jansen, Philippe; Baert, Kris; Deferm, Ludo (1997) -
Comparison between short channel bulk (silicon) and body-tied partially depleted SOI nMOS for high frequency low voltage analog circuit design
Babcock, J. A.; Francis, P.; Ølgaard, C.; Haggag, H.; Darmawan, J. A.; Archer, D. M.; Jansen, Philippe; Leeman, Marc; Schroder, D. K. (1999) -
Consistent small-signal and large-signal extraction techniques for heterojunction FET's
Jansen, Philippe; Schreurs, Dominique; De Raedt, Walter; Nauwelaers, Bart; Van Rossum, Marc (1995) -
Direct measurement of Leff and channel profile in MOSFETs using 2-D carrier profiling techniques
De Wolf, Peter; Stephenson, Robert; Biesemans, Serge; Jansen, Philippe; Badenes, Gonçal; De Meyer, Kristin; Vandervorst, Wilfried (1998) -
ESD circuit model based protection network optimisation for extended-voltage NMOS drivers
Vassilev, Vesselin; Vaschenko, V.; Jansen, Philippe; Groeseneken, Guido; Terbeek, M. (2005-10) -
Extreme voltage and current overshoots in HV snapback devices during HBM ESD stress
Linten, Dimitri; Vashchenko, Vlad; Scholz, Mirko; Jansen, Philippe; Lafonteese, David; Thijs, Steven; Sawada,; Hasebe,; Hopper, Peter; Groeseneken, Guido (2008-09) -
Far-infrared study of an InAs-GaSb quantum well
Bruelemans, P.; Schets, H.; Borghs, Gustaaf; Witters, Johan; Jansen, Philippe (1998) -
Gate stack optimisation for advanced CMOS process
Kubicek, Stefan; Vandenberghe, Geert; Schaekers, Marc; Kol'dyaev, Victor; Jansen, Philippe; Badenes, Gonçal; Deferm, Ludo; De Meyer, Kristin; Kerr, Daniel; Naem, Abdalla (1999) -
HBM parameter extraction and transient safe operating area
Linten, Dimitri; Thijs, Steven; Griffoni, Alessio; Scholz, Mirko; Chen, Shih-Hung; Lafonteese, David; Vashchenko, Vladislav; Sawada, Masanori; Concannon, Ann; Hopper, Peter; Jansen, Philippe; Groeseneken, Guido (2010-10) -
Impact of processing parameters on leakage current and defect behavior of n+p silicon junction diodes
Gramenova, Emilia; Jansen, Philippe; Simoen, Eddy; Vanhellemont, Jan; Dupas, Luc; Deferm, Ludo (1997) -
Impact of processing parameters on leakage current and defect behavior of n+p silicon junction diodes
Gramenova, Emilia; Jansen, Philippe; Simoen, Eddy; Vanhellemont, Jan; Dupas, Luc; Deferm, Ludo (1999) -
Improving the of ESD self-protection capability of Integrated power NLDMOS arrays
Vashchenko, V.; Strachan, A.; Linten, Dimitri; Lafonteese, David; Concannon, Ann; Scholz, Mirko; Thijs, Steven; Jansen, Philippe; Hopper, Peter; Groeseneken, Guido (2010) -
Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications
Thijs, Steven; Okushima, Mototsugu; Borremans, Jonathan; Jansen, Philippe; Linten, Dimitri; Scholz, Mirko; Wambacq, Piet; Groeseneken, Guido (2008) -
Investigation of instrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxides
Kubicek, Stefan; Henson, W. K.; De Keersgieter, An; Badenes, Gonçal; Jansen, Philippe; van Meer, Hans; Kerr, Daniel; Naem, Abdalla; Deferm, Ludo; De Meyer, Kristin (1999) -
Lithography options for the 32nm half pitch node and beyond
Ronse, Kurt; Jansen, Philippe; Gronheid, Roel; Hendrickx, Eric; Maenhoudt, Mireille; Goethals, Mieke; Vandenberghe, Geert (2008)