Browsing by author "Schram, Tom"
Now showing items 21-40 of 248
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Analytical model for anomalous positive bias temperature instability in La-based HfO2 nFETs based on independent characterization of charging components
Toledano Luque, Maria; Kaczer, Ben; Aoulaiche, Marc; Spessot, Alessio; Roussel, Philippe; Ritzenthaler, Romain; Schram, Tom; Thean, Aaron; Groeseneken, Guido (2013) -
Analytical model for anomalous positive bias temperature instability in La-based HfO2 nFETs based on independent characterization of charging components
Toledano Luque, Maria; Kaczer, Ben; Aoulaiche, Marc; Spessot, Alessio; Roussel, Philippe; Ritzenthaler, Romain; Schram, Tom; Thean, Aaron; Groeseneken, Guido (2013) -
Application of combinatorial methodologies for work function engineering of metal gate/high-k advanced gate stacks
Green, M.L.; Chang, Shou-Zen; De Gendt, Stefan; Schram, Tom; Hattrick-Simpers, J. (2007-09) -
Assessing the prospects of atomic layer deposition for two-dimensional materials in microelectronic applications
Groven, Benjamin; Tomczak, Yoann; Nalin Mehta, Ankit; Bender, Hugo; Zhang, Haodong; Schram, Tom; Smets, Quentin; Heyns, Marc; Caymax, Matty; Radu, Iuliana; Delabie, Annelies (2018) -
Assessment of SiGe quantum well transistors for DRAM peripheral applications
Ritzenthaler, Romain; Schram, Tom; Eneman, Geert; Mocuta, Anda; Horiguchi, Naoto; Thean, Aaron; Spessot, Alessio; Aoulaiche, Marc; Fazan, Pierre; Noh, Kyung Bong; Son, Yunik (2015) -
AVD and MOCVD TaCN-based films for gate metal applications on high-k gate dielectrics
Karim, Zia; Barbar, Ghassan; Boissiere, Olivier; Lehnen, Peer; Lohe, Christoph; Seidel, Tom; Adelmann, Christoph; Conard, Thierry; O'Sullivan, Barry; Ragnarsson, Lars-Ake; Schram, Tom; Van Elshocht, Sven; De Gendt, Stefan (2007-10) -
Band edge work function metal gates using PEALD TaCN electrodes
Maes, Jan; Swerts, Johan; Pierreux, Dieter; Machkaoutsan, Vladimir; Marcus, Steven; Milligan, Brennan; Schram, Tom; Ragnarsson, Lars-Ake; Cacciato, Antonio; Rohr, Erika; Rothschild, Aude; Hendrickx, Paul; Breuil, Laurent; Van den Bosch, Geert (2009) -
BEOL compatible WS2 transistors fully fabricated in a 300 mm pilot line
Schram, Tom; Smets, Quentin; Heyne, Markus; Groven, Benjamin; Kunnen, Eddy; Thiam, Arame; Devriendt, Katia; Delabie, Annelies; Lin, Dennis; Chiappe, Daniele; Asselberghs, Inge; Lux, Marcel; Brus, Stephan; Huyghebaert, Cedric; Sayan, Safak; Juncker, Aurélie; Caymax, Matty; Radu, Iuliana (2017) -
Bringing 2D material integration from the lab to the fab
Huyghebaert, Cedric; Schram, Tom; Brems, Steven; Asselberghs, Inge; Chiappe, Daniele; Radu, Iuliana (2017) -
Can we optimize the gate oxide quality of DRAM input/output pMOSFETs by a post-deposition treatment?
Simoen, Eddy; O'Sullivan, Barry; Ritzenthaler, Romain; Dentoni Litta, Eugenio; Schram, Tom; Horiguchi, Naoto; Claeys, Cor (2019) -
Challenges and progresses in high-k metal gate for Silicon-based advanced CMOS transistor architecture
Horiguchi, Naoto; Ragnarsson, Lars-Ake; Mertens, Hans; Arimura, Hiroaki; Ritzenthaler, Romain; Franco, Jacopo; Schram, Tom; Dekkers, Harold; Barla, Kathy; Mocuta, Dan (2017) -
Challenges for I/O towards the 3-nm node: Si/SiGe superlatttice I/O finFET in a horizontal nanowire technology and the increased ausceptibility of bulk finFET technology to single event latchup
Hellings, Geert; Mertens, Hans; Karp, James; Maillard, Pierre; Subirats, Alexandre; Simoen, Eddy; Schram, Tom; Ragnarsson, Lars-Ake; Simicic, Marko; Chen, Shih-Hung; Parvais, Bertrand; Boudier, D; Cretu, B; Machillot, J; Pena, V; Sun, S; Yoshida, N; Kim, N; Mocuta, Anda; Linten, Dimitri; Hart, Michael; Horiguchi, Naoto (2018) -
Challenges in integration of metal gate high-k dielectrics gate stacks
Tsai, W.; Ragnarsson, Lars-Ake; Schram, Tom; De Gendt, Stefan; Heyns, Marc (2004) -
Challenges of large area integration of 2D materials in CMOS line
Huyghebaert, Cedric; Schram, Tom; Smets, Quentin; Chiappe, Daniele; Asselberghs, Inge; Brems, Steven; Verguts, Ken; Marinov, Daniil; Pantouvaki, Marianna (2018) -
Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits
Schram, Tom; Sutar, Surajit; Radu, Iuliana; Asselberghs, Inge (2022-12-01) -
Challenges with respect to high-k/metal gate stack etching and cleaning
Vos, Rita; Arnauts, Sophia; Bovie, Inge; Onsia, Bart; Garaud, Sylvain; Xu, Kaidong; Yu, HongYu; Kubicek, Stefan; Rohr, Erika; Schram, Tom; Veloso, Anabela; Conard, Thierry; Leunissen, Peter; Mertens, Paul (2007) -
Characterization of TaCl5-based ALD TaN films in metal gate stacks
Dekkers, Harold; Ragnarsson, Lars-Ake; Schram, Tom; Horiguchi, Naoto (2018) -
Charge characterisation in metal-gate/high-k layers: Effect of post-deposition annealing and gate electrode
O'Sullivan, Barry; Pourtois, Geoffrey; Kaushik, Vidya; Schram, Tom; Kittl, Jorge; Pantisano, Luigi; De Gendt, Stefan; Heyns, Marc (2007-07) -
Chemical profiling with photoemission: a comparison between angle-resolved XPS and high-energy photoemission on full gate stacks
Conard, Thierry; Schram, Tom; Adelmann, Christoph; Woicik, J. (2011) -
Cleaning and strip requirement for metal gate based CMOS integration
Schram, Tom; Sebaai, Farid; Claes, Martine; Vos, Rita; Wada, Masayuli; Rohr, Erika; Kubicek, Stefan (2009)