Browsing Articles by imec author "914cd26465c3df81fb503dfd50029e58a8269dd0"
Now showing items 1-18 of 18
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A complementary high-voltage technology based on n-type CdSe:In and p-type Ge:Cu thin film transistors
De Cubber, A. M.; De Smet, Herbert; De Vos, Joeri; Carchon, Nadine; Van Calster, Andre (1996) -
A new scalable self-aligned dual-bit split-gate charge trapping memory device
Breuil, Laurent; Haspeslagh, Luc; Blomme, Pieter; Wellekens, Dirk; De Vos, Joeri; Lorenzini, Martino; Van Houdt, Jan (2005) -
A study on substrate noise coupling among TSVs in 3D chip stack
Araga, Yuuki; Nagata, Makoto; De Vos, Joeri; Van der Plas, Geert; Beyne, Eric (2018) -
Advanced experimental Back-End-Of-Line (BEOL) stability test: measurements and simulations
Vanstreels, Kris; Cherman, Vladimir; Gonzalez, Mario; De Wolf, Ingrid; Van der Plas, Geert; De Vos, Joeri; Boemmels, Juergen; Tokei, Zsolt (2015) -
Anomalous C-V inversion in TSV's: The problem and its cure
Stucchi, Michele; De Vos, Joeri; Jourdain, Anne; Li, Yunlong; Van der Plas, Geert; Croes, Kristof; Beyne, Eric (2018) -
Effect of test structure on electromigration characteristics in 3D-TSV stacked devices
Oba, Yoshiyuki; De Messemaeker, Joke; Tyrovouzi, Anna-Maria; Miyamori, Yuichi; De Vos, Joeri; Wang, Teng; Beyer, Gerald; Beyne, Eric; De Wolf, Ingrid; Croes, Kristof (2015) -
Etch process modules development and integration in 3D-SOC applications
Tutunjyan, Nina; Sardo, Stefano; De Vos, Joeri; Van Huylenbroeck, Stefaan; Jourdain, Anne; Peng, Lan; Inoue, Fumihiro; Rassoul, Nouredine; Beyer, Gerald; Beyne, Eric; Miller, Andy; Piumi, Daniele (2018) -
Experimental characterization of the vertical and lateral heat transfer in 3D stacked IC packages
Oprins, Herman; Cherman, Vladimir; Van der Plas, Geert; De Vos, Joeri; Beyne, Eric (2016-03) -
First demonstration of hybrid CMOS imagers with simultaneous very low crosstalk and high-broadband quantum efficiency
Minoglou, Kiki; De Munck, Koen; De Vos, Joeri; Sabuncuoglu Tezcan, Deniz; Van Hoof, Chris; De Moor, Piet (2012) -
High voltage CdSe-Ge TFT driver circuits for passive AC-TFEL displays
De Vos, Joeri; De Smet, Herbert; De Cubber, A.; Van Calster, Andre (1999) -
Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects
Kljucar, Luka; Gonzalez, Mario; Croes, Kristof; De Wolf, Ingrid; De Messemaeker, Joke; Murdoch, Gayle; Nolmans, Philip; De Vos, Joeri; Boemmels, Juergen; Tokei, Zsolt (2017) -
In-line metrology for characterization and control of extreme wafer thinning of bonded wafers
Liebens, Maarten; Jourdain, Anne; De Vos, Joeri; Vandeweyer, Tom; Miller, Andy; Beyne, Eric; Li, Shifang; Bast, Gerard; Stoerring, Moritz; Hiebert, Stephen; Cross, Andrew (2019) -
Influence of Si wafer thinning processes on (Sub)surface defects
Inoue, Fumihiro; Jourdain, Anne; Peng, Lan; Phommahaxay, Alain; De Vos, Joeri; Rebibis, Kenneth June; Miller, Andy; Sleeckx, Erik; Beyne, Eric; Uedono, Akira (2017) -
New model for the characterization and simulation of TFTs in all operating regions
De Smet, Herbert; De Baets, J.; De Cubber, A. M.; De Vos, Joeri; Van Calster, Andre; Vanfleteren, Jan (1995) -
On the processing aspects of high performance hybrid backside
De Vos, Joeri; De Munck, Koen; Minoglou, Kiki; Ramachandra Rao, Padmakumar; Erismis, Mehmet Akif; De Moor, Piet; Sabuncuoglu Tezcan, Deniz (2011) -
Optical beam-based defect localization methodologies for open and short failures in micrometer-scale 3-D TSV interconnects
Jacobs, Kristof J.P.; Li, Yunlong; Stucchi, Michele; De Wolf, Ingrid; Van Huylenbroeck, Stefaan; De Vos, Joeri; Beyne, Eric (2020) -
Performance and reliability of HfALOx-based interpoly dielectrics for floating-gate flash memory
Govoreanu, Bogdan; Wellekens, Dirk; Haspeslagh, Luc; Brunco, David; De Vos, Joeri; Ruiz Aguado, Daniel; Blomme, Pieter; van der Zanden, Koen; Van Houdt, Jan (2008) -
Scaling effects in dual-bit split-gate memory devices
Breuil, Laurent; Haspeslagh, Luc; Lorenzini, Martino; De Vos, Joeri; Van Houdt, Jan (2005-11)