Browsing by Author "Chen, Rongmei"

3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes

A Modeling Study of Stacked Cu-CNT TSV on Electrical, Thermal, and Reliability Analysis

A Modeling Study on Electrical and Thermal Behavior of CNT TSV for Multilayer Structure

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part I: CNFET Transistor Optimization

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part II: CNT Interconnect Optimization

Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node

Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited)

Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs

Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node

Heavy-ion and pulsed laser induced single-event double transients in nanometer inverter chain

Increasing Functionality of Wafer's Backside: Analysis of Si and WS2 Backside Power-Switch

Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling

Insights into Scaled Logic Devices Connected from Both Wafer Sides

IR-Drop Analysis of Hybrid Bonded 3D-ICs with Backside Power Delivery and mu- & n- TSVs

Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network

Pushing carbon nanotube circuits below the 10-nm node

Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails