Browsing by Author "Degroote, Bart"

A 0.314mm2 6T-SRAM cell built with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography

A functional 41-stage ring oscillator using scaled FinFET devices with 25nm gate lengths and 10nm Fin widths applicable for the 45nm CMOS node

A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM

Challenges in patterning 45nm node multiple-gate devices and SRAM cells

CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

Doubling or quadrupling MuGFET Fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography

Integration challenges for multi-gate devices

Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274μm² 6T-SRAM cell and advanced CMOS logic circuits

Misoriented domains in 0001)-GaN/(111)-Ge grown by molecular beam epitaxy

NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics

Optimization of low-temperature silicon nitride processes for improvement of device performance

Optimization of low-tempurature silicon nitride processes for improvement of device performance

Plasma etching of deep trenches in Si

Solid phase epitaxy versus random nucleation and growth in sub-20 nm wide fin field-effect transistors

Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density

The etchback approach: enlarged process window for MuGFET gate etching