Browsing by Author "Goodwin, Michael"
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Publication 25% drive current improvement for p-type Multiple Gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions
Proceedings paper2005, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2005, p.194-195Publication A disorder-controlled-kinetics model for Negative Bias Temperature Instability and its experimental verification
Proceedings paper2005-04, Proceedings International Reliability Physics Symposium, 17/04/2005, p.381-387Publication A functional 41-stage ring oscillator using scaled FinFET devices with 25nm gate lengths and 10nm Fin widths applicable for the 45nm CMOS node
Journal article2004-08, IEEE Electron Device Letters, (25) 8, p.568-570Publication Analysis of the parasitic S/D resistance in multiple-gate FETs
Journal article2005, IEEE Trans. Electron Devices, (52) 6, p.1132-1140Publication CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach
Proceedings paper2005, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2005, p.198-199Publication Demonstration of recessed SiGe S/D and inserted metal gate on HfO2 for high performance pFETs
Proceedings paper2005-12, Technical Digest International Electron Devices Meeting (IEDM), 5/12/2005, p.907-910Publication Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification
Proceedings paper2005, Proceedings 43rd Annual IEEE International Reliability Physics Symposium, 17/04/2005, p.381-387Publication GIDL (gate-induced drain leakage) and parasitic Schottky barrier leakage elimination in aggressively scaled HfO2/TiN FiNFET devices
Proceedings paper2005, Technical Digest International Electron Devices Meeting (IEDM), 5/12/2005, p.30/05/2001-30/05/2004Publication Integration challenges for multi-gate devices
Proceedings paper2005, Proceedings International Conference on IC Design and Technology - ICICDT, 9/05/2005, p.187-194Publication Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274μm² 6T-SRAM cell and advanced CMOS logic circuits
Proceedings paper2005, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2005, p.106-107Publication Minimization of MuGFET source/drain resistance using wrap-around NiSi contacts
Proceedings paper2005-04, 6th European Conference of Ultimate Integration of Silicon, 7/04/2005Publication Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions
;Dixit, Abhisek ;Rooyackers, Rita ;Leys, Frederik ;Kaiser, Monja ;Weemaes, R.Ferain, IsabelleProceedings paper2005, Proceedings of the 35th European Solid-State Device Research Conference - ESSDERC, 12/09/2005, p.445-448Publication NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics
Proceedings paper2005, Proceedings IEEE VLSI-TSA International Symposium on VLSI Technology, 25/04/2005, p.136-137Publication On the scalability of source/drain current enhancement in thin film sSOI
Proceedings paper2005, Proceedings of the 35th European Solid-State Device Research Conference - ESSDERC, 13/09/2005, p.301-304Publication Parasitic source/drain resistance reduction in N-channel SOI MuGFETs with 15nm wide fins
Proceedings paper2005-10, Proceedings of the IEEE International SOI Conference, 3/10/2005, p.226-228Publication Performance improvement of tall triple gate devices with strained SiN layers
Journal article2005-11, IEEE Electron Device Letters, (26) 11, p.820-822Publication Tall triple-gate device with TiN/HfO2 gate stack
Proceedings paper2005, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2005, p.108-109Publication Temperature dependence of the negative bias temperature instability in the framework of dispersive transport
Journal article2005, Applied Physics Letters, (86) 14, p.143506-143506-3Publication The influence of recovery and temperature on the NBTI power-law exponent
Oral presentation2004, Semiconductor Interface Specialists Conference - SISCPublication Towards optimally shaped fins in P-channel tri-gate FETs: Can fin height be reduced further?
Proceedings paper2005, Proceedings IEEE VLSI-TSA International Symposium on VLSI Technology, 25/04/2005, p.112-113