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Browsing by Author "Goodwin, Michael"

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    25% drive current improvement for p-type Multiple Gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions

    Verheyen, Peter  
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    Collaert, Nadine  
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    Rooyackers, Rita
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    Loo, Roger  
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    Shamiryan, Denis
    Proceedings paper
    2005, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2005, p.194-195
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    A disorder-controlled-kinetics model for Negative Bias Temperature Instability and its experimental verification

    Kaczer, Ben  
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    Arkhipov, Vladimir
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    Degraeve, Robin  
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    Collaert, Nadine  
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    Groeseneken, Guido  
    Proceedings paper
    2005-04, Proceedings International Reliability Physics Symposium, 17/04/2005, p.381-387
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    A functional 41-stage ring oscillator using scaled FinFET devices with 25nm gate lengths and 10nm Fin widths applicable for the 45nm CMOS node

    Collaert, Nadine  
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    Dixit, Abhisek
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    Goodwin, Michael
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    Kottantharayil, Anil
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    Rooyackers, Rita
    Journal article
    2004-08, IEEE Electron Device Letters, (25) 8, p.568-570
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    Analysis of the parasitic S/D resistance in multiple-gate FETs

    Dixit, Abhisek
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    Kottantharayil, Anil
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    Collaert, Nadine  
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    Goodwin, Michael
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    Jurczak, Gosia  
    Journal article
    2005, IEEE Trans. Electron Devices, (52) 6, p.1132-1140
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    CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

    Kottantharayil, Anil
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    Verheyen, Peter  
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    Collaert, Nadine  
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    Dixit, Abhisek
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    Kaczer, Ben  
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    Snow, Jim
    Proceedings paper
    2005, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2005, p.198-199
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    Demonstration of recessed SiGe S/D and inserted metal gate on HfO2 for high performance pFETs

    Verheyen, Peter  
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    Eneman, Geert  
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    Rooyackers, Rita
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    Loo, Roger  
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    Eeckhout, Lieve
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    Rondas, Dirk  
    Proceedings paper
    2005-12, Technical Digest International Electron Devices Meeting (IEDM), 5/12/2005, p.907-910
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    Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification

    Kaczer, Ben  
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    Arkhipov, Vladimir
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    Degraeve, Robin  
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    Collaert, Nadine  
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    Groeseneken, Guido  
    Proceedings paper
    2005, Proceedings 43rd Annual IEEE International Reliability Physics Symposium, 17/04/2005, p.381-387
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    GIDL (gate-induced drain leakage) and parasitic Schottky barrier leakage elimination in aggressively scaled HfO2/TiN FiNFET devices

    Hoffmann, Thomas Y.
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    Doornbos, Gerben  
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    Ferain, Isabelle
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    Collaert, Nadine  
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    Zimmerman, Paul
    Proceedings paper
    2005, Technical Digest International Electron Devices Meeting (IEDM), 5/12/2005, p.30/05/2001-30/05/2004
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    Integration challenges for multi-gate devices

    Collaert, Nadine  
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    Brus, Stephan  
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    De Keersgieter, An  
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    Dixit, Abhisek
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    Ferain, Isabelle
    Proceedings paper
    2005, Proceedings International Conference on IC Design and Technology - ICICDT, 9/05/2005, p.187-194
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    Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274μm² 6T-SRAM cell and advanced CMOS logic circuits

    Witters, Liesbeth  
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    Collaert, Nadine  
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    Nackaerts, Axel
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    Demand, Marc  
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    Demuynck, Steven  
    Proceedings paper
    2005, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2005, p.106-107
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    Minimization of MuGFET source/drain resistance using wrap-around NiSi contacts

    Dixit, Abhisek
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    Kottantharayil, Anil
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    Brus, Stephan  
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    Rooyackers, Rita
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    Goodwin, Michael
    Proceedings paper
    2005-04, 6th European Conference of Ultimate Integration of Silicon, 7/04/2005
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    Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions

    Dixit, Abhisek
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    Rooyackers, Rita
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    Leys, Frederik
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    Kaiser, Monja
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    Weemaes, R.
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    Ferain, Isabelle
    Proceedings paper
    2005, Proceedings of the 35th European Solid-State Device Research Conference - ESSDERC, 12/09/2005, p.445-448
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    NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics

    Henson, Kirklen
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    Collaert, Nadine  
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    Demand, Marc  
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    Goodwin, Michael
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    Brus, Stephan  
    Proceedings paper
    2005, Proceedings IEEE VLSI-TSA International Symposium on VLSI Technology, 25/04/2005, p.136-137
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    On the scalability of source/drain current enhancement in thin film sSOI

    Augendre, Emmanuel
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    Eneman, Geert  
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    De Keersgieter, An  
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    Simons, Veerle  
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    De Wolf, Ingrid  
    Proceedings paper
    2005, Proceedings of the 35th European Solid-State Device Research Conference - ESSDERC, 13/09/2005, p.301-304
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    Parasitic source/drain resistance reduction in N-channel SOI MuGFETs with 15nm wide fins

    Dixit, Abhisek
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    Ferain, Isabelle
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    De Meyer, Kristin  
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    Kottantharayil, Anil
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    Collaert, Nadine  
    Proceedings paper
    2005-10, Proceedings of the IEEE International SOI Conference, 3/10/2005, p.226-228
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    Performance improvement of tall triple gate devices with strained SiN layers

    Collaert, Nadine  
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    De Keersgieter, An  
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    Kottantharayil, Anil
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    Rooyackers, Rita
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    Eneman, Geert  
    Journal article
    2005-11, IEEE Electron Device Letters, (26) 11, p.820-822
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    Tall triple-gate device with TiN/HfO2 gate stack

    Collaert, Nadine  
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    Demand, Marc  
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    Ferain, Isabelle
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    Lisoni, Judit
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    Singanamalla, Raghunath
    Proceedings paper
    2005, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2005, p.108-109
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    Temperature dependence of the negative bias temperature instability in the framework of dispersive transport

    Kaczer, Ben  
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    Arkhipov, Vladimir
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    Degraeve, Robin  
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    Collaert, Nadine  
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    Groeseneken, Guido  
    Journal article
    2005, Applied Physics Letters, (86) 14, p.143506-143506-3
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    The influence of recovery and temperature on the NBTI power-law exponent

    Kaczer, Ben  
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    Degraeve, Robin  
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    Arkhipov, Vladimir
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    Collaert, Nadine  
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    Groeseneken, Guido  
    Oral presentation
    2004, Semiconductor Interface Specialists Conference - SISC
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    Towards optimally shaped fins in P-channel tri-gate FETs: Can fin height be reduced further?

    Dixit, Abhisek
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    Kottantharayil, Anil
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    Mercha, Abdelkarim  
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    Collaert, Nadine  
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    Brus, Stephan  
    Proceedings paper
    2005, Proceedings IEEE VLSI-TSA International Symposium on VLSI Technology, 25/04/2005, p.112-113

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