Browsing by Author "Jurczak, Gosia"
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Publication 10x10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation
Proceedings paper2011, IEEE International Electron Devices Meeting - IEDM, 5/12/2011, p.729-732Publication 25% drive current improvement for p-type Multiple Gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions
Proceedings paper2005, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2005, p.194-195Publication 2D and 3D Fully-depleted extension-less devices for advanced logic and memory applications
Proceedings paper2012-09, International Conference on Solid State Devices and Materials - SSDM, 25/09/2012Publication 45nm LSTP FET with FUSI gate on PVD-HfO2 with excellent drivability by advanced PDA treatment
Journal article2005, Microelectronic Engineering, 80, p.7-10Publication 45nm nMOSFET with metal gate on thin SiON driving 1150μA/μm and off-state of 10nA/μm
; ; Publication 90nm W\Al2O3\TiW\Cu 1T1R CBRAM cell showing low-power, fast and disturb-free operation
Proceedings paper2013, 5th IEEE International Memory Workshop - IMW, 26/05/2013, p.26-29Publication A 0.314mm2 6T-SRAM cell built with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography
Proceedings paper2004-12, Technical Digest International Electron Devices Meeting - IEDM, 13/12/2004, p.269-272Publication A consistent model for oxide trap profiling with the trap spectroscopy by charge injection and sensing (TSCIS) technique
; ; ; ; Zahid, MohammedJournal article2010, Solid-State Electronics, (54) 11, p.1384-1391Publication A functional 41-stage ring oscillator using scaled FinFET devices with 25nm gate lengths and 10nm Fin widths applicable for the 45nm CMOS node
Journal article2004-08, IEEE Electron Device Letters, (25) 8, p.568-570Publication A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM
Publication A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C
Proceedings paper2010, IEEE Symposium on VLSI Technology, 15/06/2010, p.161-162Publication A novel CBRAM integration using subtractive dry-etching process of Cu enabling high-performance memory scaling down to 10nm node
Proceedings paper2015, IEEE Symposium on VLSI Technology, 15/06/2015, p.134-135Publication A novel low-voltage biasing scheme for double gate FBC achieving 5s retention and 10^16 endurance at 85°C
Proceedings paper2010, IEEE International Elecrton Devices Meeting - IEDM, 6/12/2010, p.288-291Publication A novel PEALD tunnel dielectric for three-dimensional non-volatile charge-trapping technology
Journal article2011, Electrochemical and Solid-State Letters, (14) 7, p.271-273Publication A novel PEALD tunnel dielectric for three-dimensional non-volatile charge-trapping technology
Proceedings paper2010, IEEE Semiconductor Interface Specialists Conference - SISC, 2/12/2010Publication A novel trapping/detrapping model for defect profiling in high-k materials using the two-pulse capacitance-voltage technique
Journal article2010, IEEE Transactions on Electron Devices, (57) 10, p.2726-2735Publication A systematic study of trade-offs in engineering a locally strained pMOSFET
Proceedings paper2004, Technical Digest International Electron Devices Meeting - IEDM, 13/12/2004, p.1055-1058Publication A thermally stable and high-performance 90nm Al2O3\Cu-based 1T1R CBRAM cell
Journal article2013, IEEE Transactions on Electron Devices, (60) 11, p.3690-3695Publication a-VMCO: a novel forming-free, self-rectifying analog memory cell with low-current operation, nonfilamentary switching and excellent variability
; ; ; ; Proceedings paper2015, IEEE Symposium on VLSI Technology, 16/06/2015, p.132-133Publication Ab initio modeling of oxygen-vacancy formation in doped-HfOx RRAM: effects of oxide phases, stoichiometry and dopant concentrations
Journal article2015, Applied Physics Letters, (107) 1, p.13504