Browsing by Author "Lindsay, Richard"
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Publication A comparison of spike, flash, SPER and laser annealing for 45nm CMOS
Proceedings paper2003, CMOS Front-End Materials and Process Technology, 21/04/2003, p.261-266Publication A new technique to fabricate ultra-shallow-junctions, combining in-situ vapour HCl etching and in-situ doped epitaxial SiGe re-growth
Journal article2004, Applied Surface Science, (224) 1_4, p.63-67Publication A new technique to fabricate Ultra-Shallow-Junctions, combining in-situ vapour HCl etching and in-situ doped epitaxial SiGe re-growth
Meeting abstract2003-01, Book of Abstracts 1st International SiGe Technology and Device Meeting - ISTDM, 15/01/2003, p.159-160Publication A practical baseline process for advanced CMOS devices research
Proceedings paper2003, Proceedings 33rd European Solid-State Device Research Conference - ESSDERC, 16/09/2003, p.27-30Publication Advanced front-end processes for the 45nm CMOS technology node
Oral presentation2004, E-MRS Spring Meeting Symposium B: Materials Science Issues in Advanced CMOS Source-Drain EngineeringPublication Advanced PMOS device architecture for highly-doped ultra-shallow junctions
Journal article2004, Japanese J. of Appl. Phys. Part 1, (43) 4B, p.1778-1783Publication An (un)solvable problem in SIMS: B-interfacial profiling
Journal article2003, Applied Surface Science, 203-204, p.371-376Publication Analysis of junctions formed in strained Si/SiGe substrates
; ; ; ;Lindsay, Richard; Proceedings paper2004, High-Mobility Group-IV Materials and Devices, 12/04/2004, p.187-192Publication Analysis of silicide / diffusion contact resistance making use of transmission line stuctures
Proceedings paper2002, Silicon Materials - Processing, Characterization, and Reliability, 1/04/2002, p.53-58Publication Applications of Ni-based silicides to 45 nm CMOS and beyond
Proceedings paper2004, Silicon Front-End Junction Formation - Physics and Technology, 12/04/2004, p.31-42Publication Arsenic junction thermal stability and high-dose boron-pocket activation during SPER in nMOS transistors
Journal article2007, IEEE Electron Device Letters, (28) 3, p.198-200Publication Carrier illumination for characterization of ultra-shallow doping profiles
Proceedings paper2003, Ultra Shallow Junctions. 7th Int. Worksh. Fabrication, Characterization and Modeling of Ultra Shallow Doping Profiles in Semic., 27/04/2003, p.321-330Publication Carrier illumination for characterization of ultrashallow doping profiles
Journal article2004-02, Journal of Vacuum Science and Technology B, (22) 1, p.439-443Publication Carrier illumination for monitoring of CMOS ultra-shallow junctions
Oral presentation2002, E-MRS Spring Meeting Symposium E: Advanced Characterisation of Semiconductor Materials and DevicesPublication Challenges in scaling of CMOS devices towards 65nm node
Proceedings paper2003-06, Diagnostic and Yield, 23/06/2003Publication Channel engineering and junction overlap issues for ultra-shallow junctions formed by SPER in the 45 nm CMOS technology node
Proceedings paper2004-04, Silicon Front-End Junction Formation - Physics and Technology, 8/04/2004, p.455-460Publication Channel engineering towards a full low temperature process solution for the 45 nm technology node
Proceedings paper2004, Proceedings of the 34th European Solid-State Device Research Conference - ESSDERC, 21/09/2004, p.225-229Publication Characterization of the B and As pile-up at the Si-SiO2 interface
Proceedings paper2003, Ultra Shallow Junctions. 7th Int. Worksh. Fabrication, Characterization and Modeling of Ultra Shallow Doping Profiles in Semic., 27/04/2003, p.399-404Publication Chemical and electrical dopant evolution during solid phase epitaxial regrowth
Proceedings paper2003, Ultra Shallow Junctions. 7th Int. Worksh. Fabrication, Characterization and Modeling of Ultra Shallow Doping Profiles in Semic., 28/04/2003, p.227-233Publication Chemical and electrical dopant profiling for P-type junctions formed by solid phase epitaxial regrowth
Proceedings paper2003, Characterization and Metrology for ULSI, 24/03/2003