Browsing by Author "Matagne, Philippe"
- Results per page
- Sort Options
Publication 12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices
; ; ; ; Huynh Bao, TrongProceedings paper2019, 2019 Symposium on VLSI Technology, 9/06/2019, p.T15-1Publication 3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters
Proceedings paper2020, IEEE Symposium on VLSI Technology and Circuits, JUN 15-19, 2020Publication A Scalable One Dimensional Silicon Qubit Array with Nanomagnets
Proceedings paper2020, IEEE International Electron Devices Meeting (IEDM), DEC 12-18, 2020Publication Accurate prediction of device performance in sub-10nm WFIN FinFETs using scalpel SSRM-based calibration of process simulations
Proceedings paper2016, International Conference on Simulation of Semiconductor Processes and Devices - SISPAD, 6/09/2016, p.287-290Publication Advances on doping strategies for triple-gate FinFETs and lateral gate-all-around nanowire FETs and their impact on device performance
Journal article2017, Materials Science in Semiconductor Processing, 62, p.2-12Publication Benchmarking time-dependent variability of junctionless nanowire FETs
Proceedings paper2017, International Reliability Physics Symposium - IRPS, 2/04/2017, p.2D-6.1-2D-6.7Publication Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications
Proceedings paper2019, 2019 Symposia on VLSI Technology and Circuits, 9/06/2019, p.T56-T57Publication Challenges and opportunities for vertical nanowire FETs: device design and fabrication
Proceedings paper2018, 50th International Conference on Solid State Devices and Materials - SSDM, 9/09/2018, p.159-160Publication Challenges and opportunities of vertical FET devices using 3D circuit design layouts
Proceedings paper2016, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference - S3S, 10/10/2016, p.1-3Publication Challenges on surface conditioning in 3D device architectures: triple-gate FinFETs, gate-all-around lateral and vertical nanowire FETs
Proceedings paper2017, 232nd ECS Fall Meeting - 15th International Symposium on Semiconductor Cleaning Science and Technology - SCST15, 1/10/2017, p.3-20Publication Challenges on surface conditioning in 3D device architectures: triple-gate finFETs, gate-all-around lateral and vertical nanowireFETs
Meeting abstract2017, 15th International Symposium on Semiconductor Cleaning Science and Technology at the 232nd ECS Fall Meeting, 1/10/2017, p.1055Publication Co-integration Process Compatible Input/Output (I/O) Device Options for GAA Nanosheet Technology
Proceedings paper2022, 52nd IEEE European Solid-State Device Research Conference (ESSDERC), SEP 19-22, 2022, p.265-268Publication Combining TCAD and advanced metrology techniques to support device integration towards N3
Proceedings paper2021, 20th International Workshop on Junction Technology (IWJT), JUN 10-11, 2021, p.84-87Publication Compact thermally stable high voltage FinFET with 40 nm tox and lateral break-down >35 V for 3D NAND flash periphery application
Journal article2024, JAPANESE JOURNAL OF APPLIED PHYSICS, (63) 3, p.Art. 03SP12Publication Device-, circuit- & block-level evaluation of CFET in a 4 track library
Proceedings paper2019, 2019 Symposia on VLSI Technology and Circuits, 9/06/2019, p.T204-T205Publication DTCO and TCAD for a 12 layer-EUV ultra-scaled surrounding gate transistor 6T-SRAM
Proceedings paper2018, 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 24/09/2018, p.45-48Publication DTCO flow for device exploration
Meeting abstract2018, SNUG (Synopsys User Group) Europe 2018, 11/06/2018Publication DTCO of Nanosheet and Forksheet Architectures: Exploring Dielectric Walls, Contacting Schemes, and Active Regions for Optimized RO Performance
Proceedings paper2024, 8th Electron Devices Technology & Manufacturing Conference (EDTM), MAR 03-06, 2024, p.226-228Publication Exploring GAA-Nanosheet, Forksheet and GAA-Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell Height
Journal article2025, IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 13, p.769-782Publication Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node
Journal article2022, IEEE TRANSACTIONS ON ELECTRON DEVICES, (69) 6, p.3113-3117