Browsing by Author "Nackaerts, Axel"

A 0.314mm2 6T-SRAM cell built with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography

A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM

Challenges in patterning 45nm node multiple-gate devices and SRAM cells

Direct measurement of top and sidewall interface trap density in SOI FinFETs

Dose enhancement due to interconnects in deep-submicron MOSFETs exposed to X-rays

Dose enhancement due to interconnects in deep-submicron MOSFETs exposed to X-rays

Doubling or quadrupling MuGFET Fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling

FUSI specific yield monitoring enabling improved circuit performance and fast feedback to production

Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274μm² 6T-SRAM cell and advanced CMOS logic circuits

Layout options for stability tuning of SRAM cells in multi-gate=FET technologies

Litho enhancements for 45nm-node MuGFETs

Litho variations and their impact on the electrical yield of a 32nm node 6T-SRAM cell

Lithography and yield sensitivity analysis of SRAM scaling for the 32-nm node.

Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

Low-voltage scaled 6T FinFET SRAM cells

Multi-gate devices for the 32nm technology node and beyond

Multi-gate devices for the 32nm technology node and beyond

Optical extensions integration for a 0.314-μm² 45-nm node 6-transistor SRAM cell

Proof-of-concept structure for investigation of successive soft gate oxide breakdowns in two dimensions