Browsing by Author "Piumi, Daniele"
- Results per page
- Sort Options
Publication A million wafer, virtual fabrication approach to determine process capability requirements for an industry-standard 5nm BEOL two-level metal flow
Proceedings paper2016, International Conference on Simulation of Semiconductor Processes and Devices - SISPAD, 6/09/2016, p.43-46Publication A wafer-scaled III-V vertical FET fabrication by means of plasma etching
Journal article2018, Microelectronic Engineering, 192, p.14-18Publication Challenges for line width / line edge roughness (LWR/lER) improvement in Directed Self-Assembly (DSA) advanced patterning
Proceedings paper2015, DSA Symposium, 26/10/2015Publication Characterization of optical end-point detection for via reveal processing
Proceedings paper2018, IEEE 68th Electronic Components and Technology Conference - ECTC, 29/05/2018, p.1181-1187Publication Direct metal etch evaluation for advanced interconnect
Proceedings paper2017, AVS 64th International Symposium & Exhibition, 29/10/2017, p.PS-WeM2Publication Direct metal etch for advanced interconnect
Journal article2018, Journal of Vacuum Science and Technology B, (36) 3, p.3.00E+103Publication Direct metal nanowire patterning using ion beam etch
Meeting abstract2017, AVS 64th International Symposium and Exhibition, 29/10/2017, p.PS-WeM13Publication Etch challenges for chemo-expitaxy Directed Self-Assembly (DSA) LiNe flow in Fin patterning
Meeting abstract2016, Plasma Etch and Strip in Microtechnology - PESM, 9/05/2016Publication Etch process modules development and integration in 3D SOC applications
Meeting abstract2017, 10th International Workshop on Plasma Etch and Strip in Microtechnology - PESM, 19/10/2017Publication Etch process modules development and integration in 3D-SOC applications
Journal article2018, Microelectronic Engineering, 196, p.38-48Publication Exploration of a low-temperature PEALD technology to trim and smooth 193i photoresist
Proceedings paper2017, Advances in Patterning Materials and Processes XXXIV, 26/02/2017, p.101460KPublication III-V fin patterning in SADP scheme
Meeting abstract2016, Plasma Etch and Strip in Microtechnology - PESM, 9/05/2016Publication Impact of sequential infiltration synthesis (SIS) on roughness and stochastic nano-failures for EUVL patterning
; ; ; ; ; Kissoon, NicolaProceedings paper2019, Extreme Ultraviolet (EUV) Lithography X, 24/02/2019, p.109570SPublication Magnetic tunnel junctions etch and encapsulation process optimization for high-density STT-MRAM applications
Meeting abstract2016, AVS 63rd International Symposium and Exhibition, 6/11/2016, p.PS-ThP33Publication Pattern transfer challenges of the Sequential Infiltration Synthesis (SIS) of of Directed Self-Assembly (DSA) for line/space applications
Proceedings paper2016, 42nd Micro- and Nano-Engineering - MNE, 19/09/2016Publication Patterning challenges for ultimate CMOS and beyond CMOS nano-fabrication
Proceedings paper2017, iPlasmaNano-VIII, 2/07/2017Publication Patterning challenges in advanced device architectures: FinFETs to nanowire
Proceedings paper2016, Advanced Etch Technology for Nanopatterning V, 22/02/2016, p.978209Publication Practical steps towards wafer-scaled III-V vertical FETs fabrication
Meeting abstract2017, 43rd International Conference on Micro and Nanoengineering - MNE, 18/09/2017, p.232-232Publication Process window study of SAQP gratings used to pattern a dual damascene structure at 7nm technology node
Meeting abstract2016, Plasma Etch and Strip in Microtechnology - PESM, 9/05/2016Publication RIE dynamics for extreme wafer thinning applications
Meeting abstract2017, PESM, 20/10/2017