Browsing by Author "Vertommen, Johan"
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Publication 15nm HP patterning with EUV and SADP: key contributors for improvement of LWR, LER, and CDU
Proceedings paper2013, Advanced Etch Technology for Nanopatterning II, 23/02/2013, p.86850CPublication 15nm HP patterning with EUV lithography and SADP
Meeting abstract2012, 34th International Symposium on Dry Process - DPS, 15/11/2012Publication 30-nm half-pitch metal patterning using MotifTM critical dimension shrink technique and double patterning
Journal article2009, Journal of Micro/Nanolithography MEMS MOEMS, (8) 1, p.11007Publication 30nm half-pitch metal patterning using MotifTM CD shrink technique and double patterning
Proceedings paper2008, Optical Microlithography XXI, 24/02/2008, p.69242CPublication 45nm nMOSFET with metal gate on thin SiON driving 1150μA/μm and off-state of 10nA/μm
; ; Publication A novel concept for contact etch residue removal
Proceedings paper2007, Cleaning and Surface Conditioning Technology in Semiconductor Device Manufacturing 10, 7/10/2007, p.403-407Publication Characterization and residue elimination of hot aluminum etching in a transformer coupled plasma etcher
Publication Characterization of PVD TaN and ALD WNxCy copper diffusion barriers on a porous CVD low-k material
Proceedings paper2004, Advanced Metallization Conference 2003, 21/10/2003, p.723-728Publication Clean dry strip process for implanted resist using water vapor plasma
Publication Confined chemical cleaning: a novel concept evaluated for front end of line applications
Proceedings paper2008, Ultra Clean Processing of Semiconductor Surfaces VIII - UCPSS, 17/09/2006, p.121-124Publication Dry Development for 0.25 5m Top Surface Imaging
Publication Dry development for 0.25 μm top surface imaging
Publication Dry development in an O2/SO2 plasma for sub-0.18 μm top layer imaging processes
Journal article1998, Journal of Vacuum Science and Technology B, (12) 6, p.3322-3333Publication Evaluation of advanced I-line resists for practical 0.5*(l/NA) lithography
Proceedings paper1994, OCG Microlithography Seminar INTERFACE, 6/11/1994, p.105-124Publication Exploring high aspEct ratio 2μm TSV (25:1)
Proceedings paper2011-11, 64th Annual Gaseous Electronics Conference - GEC, 14/11/2011Publication III-V fin patterning in SADP scheme
Meeting abstract2016, Plasma Etch and Strip in Microtechnology - PESM, 9/05/2016Publication Implementation of high-k and metal gate materials for the 45nm node and beyond: gate patterning development
Journal article2005-06, Microelectronics Reliability, (45) 5_6, p.1007-1011Publication Implementation of high-K and metal gate materials for the 45nm node and beyond: gate patterning development
Oral presentation2004, Workshop on Dielectrics in Microelectronics - WODIMPublication Integrated silylation and dry development of resist for sub-0.15µm top surface imaging applications
Journal article1998, J. Photopolymer Science and Technology, (11) 4, p.597-612Publication Integrating high-k dielectrics: etched polysilicon or metal gates?
Journal article2003, Solid State Technology, (46) 6, p.61-64
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