Browsing by Author "Yakimets, Dmitry"

5nm: has the time for a device change come?

A comprehensive benchmark and optimization of 5-nm lateral and vertical GAA 6T-SRAMs

Benchmarking of MoS2 FETs with multigate Si-FET options for 5 nm and beyond

Built-in sheet charge as an alternative to dopant pockets in tunnel field-effect transistors

Buried power rail integration with FinFETs for ultimate CMOS scaling

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM

Device challenges for logic scaling for sub-5 nm node

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7

Device exploration of nanosheet transistors for sub-7nm technology node

Device-, circuit- & block-level evaluation of CFET in a 4 track library

Device/system performance modeling of stacked lateral NWFET logic

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling

DTCO flow for device exploration

DTCO of Nanosheet and Forksheet Architectures: Exploring Dielectric Walls, Contacting Schemes, and Active Regions for Optimized RO Performance

Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node

Extreme scaling enabled by 5 tracks cells : holistic design-device co-optimization for FinFETs and lateral nanowires

Ge Devices: a potential candidate for sub-5nm nodes?

Heterogeneous nano- to wide-scale co-integration of beyond-Si and Si CMOS devices to enhance future electronics