Browsing by author "Ritzenthaler, Romain"
Now showing items 21-40 of 128
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Buried power rail integration with FinFETs for ultimate CMOS scaling
Gupta, Anshul; Varela Pedreira, Olalla; Arutchelvan, Goutham; Zahedmanesh, Houman; Devriendt, Katia; Hanssen, Frederik; Tao, Zheng; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, Noemie; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min-Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Cousserier, Joris; Yakimets, Dmitry; Lazzarino, Frederic; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Jaysankar, Manoj; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Boemmels, Juergen; Demuynck, Steven; Tokei, Zsolt; Horiguchi, Naoto (2020) -
Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
Gupta, Anshul; Mertens, Hans; Tao, Zheng; Demuynck, Steven; Boemmels, Juergen; Arutchelvan, Goutham; Devriendt, Katia; Varela Pedreira, Olalla; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Zahedmanesh, Houman; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, N.; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Yakimets, Dmitry; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frederic; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Tokei, Zsolt; Horiguchi, Naoto (2020) -
Can we optimize the gate oxide quality of DRAM input/output pMOSFETs by a post-deposition treatment?
Simoen, Eddy; O'Sullivan, Barry; Ritzenthaler, Romain; Dentoni Litta, Eugenio; Schram, Tom; Horiguchi, Naoto; Claeys, Cor (2019) -
Challenges and progresses in high-k metal gate for Silicon-based advanced CMOS transistor architecture
Horiguchi, Naoto; Ragnarsson, Lars-Ake; Mertens, Hans; Arimura, Hiroaki; Ritzenthaler, Romain; Franco, Jacopo; Schram, Tom; Dekkers, Harold; Barla, Kathy; Mocuta, Dan (2017) -
Charge based compact modeling for bulk FinFETs
Cerdeira, Antonio; Estrada, Magali; Ritzenthaler, Romain; Franco, Jacopo; Togo, Mitsuhiro; Claeys, Cor (2012) -
Charge based DC compact modeling of bulk FinFET transistor
Cerdeira, Antonio; Garduno, Ivan; Tinoco, Julio; Ritzenthaler, Romain; Franco, Jacopo; Togo, Mitsuhiro; Chiarella, Thomas; Claeys, Cor (2013) -
CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits
Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O'Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto (2018) -
CMOS integration of thermally stable diffusion and gate replacement (D&GR) high-k/metal gate stacks in DRAM periphery transistors
Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O'Sullivan, Barry; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto (2017) -
Combining TCAD and advanced metrology techniques to support device integration towards N3
Eyben, Pierre; De Keersgieter, An; Celano, Umberto; Wouters, Lennaert; Chiarella, Thomas; Ritzenthaler, Romain; Mertens, Hans; Richard, Olivier; Paredis, Kristof; Matagne, Philippe; Mitard, Jerome; Horiguchi, Naoto; Goux, Ludovic (2021) -
Compact modeling of double and tri-gate MOSFETs
Iniguez, Benjamin; Ritzenthaler, Romain; Lime, Francois (2013) -
Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond
Ritzenthaler, Romain; Mertens, Hans; Eneman, Geert; Simoen, Eddy; Bury, Erik; Eyben, Pierre; Bufler, Fabian; Oniki, Yusuke; Briggs, Basoene; Chan, BT; Hikavyy, Andriy; Mannaert, Geert; Parvais, Bertrand; Vaisman Chasin, Adrian; Mitard, Jerome; Dentoni Litta, Eugenio; Samavedam, Sri; Horiguchi, Naoto (2021) -
Comparison of temperature dependent carrier transport in FinFET and gate-all-Around nanowire FET
Kim, Soohyun; Kim, Jungchun; Jang, Doyoung; Ritzenthaler, Romain; Parvais, Bertrand; Mitard, Jerome; Mertens, Hans; Chiarella, Thomas; Horiguchi, Naoto; Lee, Jae Woo (2020) -
Complete degradation mapping of stacked gate-all-around Si nanowire transistors considering both intrinsic and extrinsic effects
Vaisman Chasin, Adrian; Bury, Erik; Kaczer, Ben; Franco, Jacopo; Roussel, Philippe; Ritzenthaler, Romain; Mertens, Hans; Horiguchi, Naoto; Linten, Dimitri; Mocuta, Anda (2017) -
Cost effective FinFET platform for stand alone DRAM 1Y and beyond memory periphery
Spessot, Alessio; Sharan, Neha; Oh, Hyungrock; Ritzenthaler, Romain; Dentoni Litta, Eugenio; Mallik, Arindam; De Keersgieter, An; Parvais, Bertrand; Sherazi, Yasser; Machkaoutsan, Vladimir; Kim, Cheolgyu; Fazan, Pierre; Mocuta, Dan; Mocuta, Anda; Horiguchi, Naoto (2018-01) -
Development of a technique for characterizing bias temperature unstability-induced device-to-device variation at SRAM-relevant conditions
Duan, M.; Zhang, J. F.; Ji, Z.; Zhang, W. D.; Kaczer, Ben; Schram, Tom; Ritzenthaler, Romain; Groeseneken, Guido; Asenov, A. (2014) -
Device scaling model for bulk FinFETs
Medury, Aditya; Mercha, Abdelkarim; Ritzenthaler, Romain; De Keersgieter, An; Chiarella, Thomas; Collaert, Nadine; Bhat, N; Bhat, KN (2012) -
Diffusion and gate replacement: a new gate-first high-k/metal gate CMOS integration scheme suppressing gate height symmetry
Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; Caillat, Christian; Cho, Moon Ju; Simoen, Eddy; Aoulaiche, Marc; Albert, Johan; Chew, Soon Aik; Noh, Kyung Bong; Son, Yunik; Mitard, Jerome; Mocuta, Anda; Horiguchi, Naoto; Fazan, Pierre; Thean, Aaron (2016) -
Economics of semiconductor scaling – a cost analysis for advanced technology node
Mallik, Arindam; Ryckaert, Julien; Kim, Ryan Ryoung han; Debacker, Peter; Decoster, Stefan; Lazzarino, Frederic; Ritzenthaler, Romain; Horiguchi, Naoto; Verkest, Diederik; Mocuta, Anda (2019) -
ESD diodes in Bulk Si gate-all-around vertically stacked horizontal nanowire technology
Chen, Shih-Hung; Hellings, Geert; Scholz, Mirko; Linten, Dimitri; Mertens, Hans; Ritzenthaler, Romain; Boschke, Roman; Groeseneken, Guido; Horiguchi, Naoto (2016) -
Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets
Bury, Erik; Vaisman Chasin, Adrian; Kaczer, Ben; Vandemaele, M.; Tyaginov, S.; Franco, Jacopo; Ritzenthaler, Romain; Mertens, Hans; Weckx, Pieter; Horiguchi, Naoto; Linten, Dimitri (2022)