Browsing by author "Wong, Patrick"
Now showing items 1-20 of 30
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15nm HP patterning with EUV and SADP: key contributors for improvement of LWR, LER, and CDU
Xu, Kaidong; Souriau, Laurent; Hellin, David; Versluijs, Janko; Wong, Patrick; Vangoidsenhoven, Diziana; Vandenbroeck, Nadia; Dekkers, Harold; Shi, Xiaoping; Albert, Johan; Tan, Chi Lim; Vertommen, Johan; Coenegrachts, Bart; Orain, I.; Kimura, Y.; Wiaux, Vincent; Boullart, Werner (2013) -
Alternative double patterning processes: ready for (sub) 32nm hp
Wong, Patrick; Maenhoudt, Mireille; Vangoidsenhoven, Diziana; Wiaux, Vincent (2009) -
BEOL N2: M2 through SAxP process from MP21 to MP26: 193i SAQP vs EUV SADP
Hermans, Yannick; Wu, Chen; Buccheri, Nunzio; Schleicher, Filip; Versluijs, Janko; Montero Alvarez, Daniel; Dey, Bappaditya; Wong, Patrick; Rincon Delgadillo, Paulina; Park, Seongho; Tokei, Zsolt; Leray, Philippe; Halder, Sandip (2023-04-28) -
Characterization of a thermal freeze LLE double patterning process for predictive simulation
Robertson, Stewart; Wong, Patrick; Biafore, John; Vandenbroeck, Nadia; Wiaux, Vincent (2010) -
Current and future requirements for metrology and inspection for advanced patterning
Leray, Philippe; Wong, Patrick; Halder, Sandip; Foubert, Philippe (2016) -
Density limits in logic metal1 using double patterning
Wiaux, Vincent; Verhaegen, Staf; Fenger, Germain; Wong, Patrick (2009) -
Double patterning induced process bias induced for various LPL alternatives
Wong, Patrick; Vandenbroeck, Nadia; Wiaux, Vincent; Gronheid, Roel (2010) -
Efficient hybrid metrology for focus, CD, and overlay
Tel, Wim; Segers, B.; Anunciado, Roy; Zhang, Y.; Wong, Patrick; Hasan, T.; Prentice, C. (2017) -
Exploring resist options for EUV layers of IMEC N5 CMOS vehicle
Thiam, Arame; Paolillo, Sara; Lazzarino, Frederic; Ercken, Monique; Wong, Patrick; Charley, Anne-Laure (2019) -
Imaging challenges in 20nm and 14nm logic nodes: hot spots performance in Metal1 layer
Timoshkov, Vadim; Rio, David; Liu, H.; Gillijns, Werner; Wang, Jing; Wong, Patrick; Van Den Heuvel, Dieter; Wiaux, Vincent; Nikolsky, Peter; Finders, Jo (2013) -
Immersion lithography and double patterning in advanced microelectronics
Vandeweyer, Tom; Bekaert, Joost; Ercken, Monique; Gronheid, Roel; Miller, Andy; Truffert, Vincent; Verhaegen, Staf; Versluijs, Janko; Wiaux, Vincent; Wong, Patrick; Vandenberghe, Geert; Maenhoudt, Mireille (2010) -
Interactions between imaging layers during LPLE double patterning lithography
Robertson, Stewart; Wong, Patrick; De Bisschop, Peter; Vandenbroeck, Nadia; Wiaux, Vincent (2012) -
Investigation of litho1-litho2 proximity differences for a LPLE double patterning process
Wong, Patrick; De Bisschop, Peter; Robertson, Stewart; Vandenbroeck, Nadia; Biafore, John; Wiaux, Vincent; Van de Kerkhove, Jeroen (2011) -
Key contributors for improvement of line width roughness, line edge roughness, and critical dimension uniformity: 15 nm half-pitch patterning with extreme ultraviolet and self-aligned double patterning
Xu, Kaidong; Souriau, Laurent; Hellin, David; Versluijs, Janko; Wong, Patrick; Vangoidsenhoven, Diziana; Vandenbroeck, Nadia; Dekkers, Harold; Shi, Xiaoping; Albert, Johan; Tan, Chi Lim; Vertommen, Johan; Coenegrachts, Bart; Orain, Isabelle; Kimura, Yoshie; Wiaux, Vincent; Boullart, Werner (2013-09) -
LENS (Lithography Enhancement towards Nano Scale) a european project to support double exposure and double patterning technology development
Cantu, Pietro; Baldi, Livio; Piacentini, Paolo; Sytsma, Joost; Le Gratiet, Bernard; Gaugiran, Stephanie; Wong, Patrick; Miyashita, Hiroyuki; Atzei, Luisa Rita; Buch, Xavier; Verkleij, Dick; Toublan, Olivier; Perez-Murano, Francesco; Mecerreyes, David (2010) -
LENS - Lithography enhancement towards nano scale
Cantu, Pietro; Baldi, Livio; De Simone, Danilo; Piacentini, Paolo; Fliervoet, Timon; Alberga, Gerold; Le Gratiet, Bertrand; Gaugiran, Stephanie; Wong, Patrick; Miyashita, Hiroyuki; Atzei, Luisa Rita; Buch, Xavier; Verkleiji, Dick; Toublan, Olivier; Perez Murano, Francesc; Mecerreyes, David (2010) -
Litho 1-litho 2 proximity differences for s LELE and LPLE double patterning processes
Wong, Patrick; De Bisschop, Peter; Vandenbroeck, Nadia; Wiaux, Vincent; Van de Kerkhove, Jeroen; Robertson, Stewart; Biafore, John (2012) -
Litho-process-litho for 2D 32nm hp LOGIC and DRAM double patterning
Wong, Patrick; Wiaux, Vincent; Verhaegen, Staf; Vandenbroeck, Nadia (2010) -
Low temperature plasma-enhanced ALD enables cost-effective spacer defined double patterning (SDDP)
Beynet, Julien; Wong, Patrick; Miller, Andy; Locorotondo, Sabrina; Vangoidsenhoven, Diziana; Yoon, Tae-Ho; Demand, Marc; Park, Hyung-Sang; Vandeweyer, Tom; Sprey, Hessel; Yoo, Yong-Min; Maenhoudt, Mireille (2009) -
Multiple patterning...various keys for scaling
Wiaux, Vincent; Wong, Patrick; Vandenbroeck, Nadia; Bekaert, Joost; Laenens, Bart; De Bisschop, Peter; Versluijs, Janko; Vandenberghe, Geert (2010)