Browsing by author "Simicic, Marko"
Now showing items 21-40 of 45
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ESD study on a-IGZO TFT device architectures
Simicic, Marko; Hellings, Geert; Chen, Shih-Hung; Myny, Kris; Linten, Dimitri (2018-10-28) -
Experimental evidences and simulations of trap generation along the percolation path
Gerrer, Louis; Hussin, Razaidi; Amoroso, Salvatore Maria; Franco, Jacopo; Weckx, Pieter; Simicic, Marko; Horiguchi, Naoto; Kaczer, Ben; Asenov, Asen (2015) -
External I/O interfaces in sub-5nm GAA NS Technology and STCO Scaling Options
Chen, Wen Chieh; Chen, Shih-Hung; Hellings, Geert; Bury, Erik; Simicic, Marko; Wu, Zhicheng; Van der Plas, Geert; Beyne, Eric; Groeseneken, Guido (2021) -
Extraction of statistical gate oxide parameters from large MOSFET arrrays
Stampfer, Bernhard; Simicic, Marko; Weckx, Pieter; Abbasi, Arash; Kaczer, Ben; Grasser, Tibor; Waltl, Michael (2020) -
HBM and CDM ESD Performance of Advanced Silicon Photonic Components
Chen, Shih-Hung; Karp, James; Simicic, Marko; Tsiara, Artemisia; Tsaggaris, Dean; Croes, Kristof; Ban, Yoojin; Tan, Phoumra; De Heyn, Peter; Chang, Jonathan; Hart, Michael J.; Wu, Xin; Linten, Dimitri; Van Campenhout, Joris (2021-10-27) -
Low-impedance Contact CDM – Evaluation and Modeling
Simicic, Marko; Wu, Wei-Min; Chen, Shih-Hung; Jack, Nathan; Tamura, Shinichi; Shimada, Yohei; Sawada, Masanori; Linten, Dimitri (2019) -
MOSFET variability and reliability characterization array
Simicic, Marko; Putcha, Vamsi; Parvais, Bertrand; Weckx, Pieter; Kaczer, Ben; Groeseneken, Guido; Gielen, Georges; Linten, Dimitri; Thean, Aaron (2015) -
On ESD gate dielectric reliability in 14nm finFET and horizontal NW technology
Hellings, Geert; Chen, Shih-Hung; Scholz, Mirko; Simicic, Marko; Schram, Tom; Ragnarsson, Lars-Ake; Horiguchi, Naoto; Linten, Dimitri (2018) -
Optimization of wafer-level low-impedance contact CDM testers
Simicic, Marko; Wu, Wei-Min; Jack, Nathan; Tamura, Shinichi; Shimada, Yohei; Sawada, Masanori; Chen, Shih-Hung (2020-11) -
Recent insights in CMOS reliability characterization by the use of degradation maps
Bury, Erik; Vaisman Chasin, Adrian; Kaczer, Ben; Chuang, Kent; Franco, Jacopo; Simicic, Marko; Weckx, Pieter; Linten, Dimitri (2018) -
Reliability aware simulation flow: from TCAD calibration to circuit level analysis
Hussin, Razzaidi; Gerrer, Louis; Ding, Jie; Amaroso, Salvatore; Wang, Liping; Simicic, Marko; Weckx, Pieter; Franco, Jacopo; Vanderheyden, Annelies; Vanhaeren, Danielle; Horiguchi, Naoto; Kaczer, Ben; Asenov, Asen (2015) -
Reliability-aware simulation and validation for analog/mixed-signal circuits in sub-32nm CMOS
Simicic, Marko (2018-08) -
Scaling CMOS beyond Si FinFET: an analog/RF perspective
Parvais, Bertrand; Hellings, Geert; Simicic, Marko; Weckx, Pieter; Mitard, Jerome; Jang, Doyoung; Deshpande, Veeresh Vidyadhar; van Liempd, Barend; Veloso, Anabela; Vandooren, Anne; Waldron, Niamh; Wambacq, Piet; Collaert, Nadine; Verkest, Diederik (2018) -
Self-heating-aware CMOS reliability characterization using degradation maps
Bury, Erik; Vaisman Chasin, Adrian; Kaczer, Ben; Chuang, Kent; Franco, Jacopo; Simicic, Marko; Weckx, Pieter; Linten, Dimitri (2018) -
Si/SiGe superlattice I/O finFETs in a vertically-stacked gate-all-around horizontal nanowire technology
Hellings, Geert; Mertens, Hans; Subirats, Alexandre; Simoen, Eddy; Schram, Tom; Ragnarsson, Lars-Ake; Simicic, Marko; Chen, Shih-Hung; Parvais, Bertrand; Boudier, Dimitri; Cretu, Bogdan; Machillot, Jerome; Pena, Vanessa; Sun, S.; Yoshida, N.; Kim, N.; Mocuta, Anda; Linten, Dimitri; Horiguchi, Naoto (2018) -
Single Event Latchup or Multi Event Latchup - How far can you push it?
Hellings, Geert; Truijen, Brecht; Simicic, Marko; Chen, Shih-Hung (2020) -
Smart-array for pipelined BTI characterization
Putcha, Vamsi; Simicic, Marko; Weckx, Pieter; Parvais, Bertrand; Kaczer, Ben; Franco, Jacopo; Linten, Dimitri; Verkest, Diederik; Thean, Aaron; Groeseneken, Guido (2015) -
Statistical assessment of the full VG/VD degradation space using dedicated device arrays
Bury, Erik; Kaczer, Ben; Chuang, Kent; Franco, Jacopo; Weckx, Pieter; Vaisman Chasin, Adrian; Simicic, Marko; Linten, Dimitri; Groeseneken, Guido (2017) -
Statistical characterization of BTI and RTN using pMOS arrays
Stampfer, Bernhard; Simicic, Marko; Weckx, Pieter; Abbasi, Arash; Kaczer, Ben; Grasser, Tibor; Waltl, Michael (2019) -
Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow
Hussin, Razaidi; Gerrer, Louis; Ding, Jie; Wang, Liping; Amoroso, Salvatore; Cheng, Binjie; Weckx, Pieter; Simicic, Marko; Franco, Jacopo; Vanderheyden, Annelies; Vanhaeren, Danielle; Horiguchi, Naoto; Kaczer, Ben; Asenov, Asen (2015)