Recently added

An integrated photonics reservoir computing approach to signal equalization for telecommunications

Katumba, Andrew; Schneider, Bendix; Dambre, Joni; Bienstman, Peter (2016)

Uniform large-area slot-die coating of soluble metal oxide semiconductor towards mass production of high-performance TFT backplanes

Katsouras, lias; Maas, Joris; van der Steen, Jan Laurens; Gelinck, Gerwin; Takata, Ryo; Marinkovic, Marko; Neumann, Anita; Pham, Duy-Vu; Anselmann, Ralf; Ke, Tung Huei; Smout, Steve; Schols, Sarah (2016)

Performance and reliability impact of copper plasticity in backside TSV-last fabrication process

Karmarkar, Aditya P.; Guo, Wei; Xu, Xiaopeng; Van der Plas, Geert; Van Huylenbroeck, Stefaan; Gonzalez, Mario; Absil, Philippe; El Sayed, Karim; Beyne, Eric (2016)

Design strategy for integrating DSA via patterning in sub-7 nm interconnects

Karageorgos, Ioannis; Ryckaert, Julien; Tung, C. Maryann; Wong, H.-S. Philip; Gronheid, Roel; Bekaert, Joost; Croes, Kris; Karageorgos, Evangelos; Vandenberghe, Geert; Stucchi, Michele; Dehaene, Wim (2016)

Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits

Karageorgos, Ioannis; Ryckaert, Julien; Gronheid, Roel; Tung, Maryann C.; Wong, H.-S. Philip; Karageorgos, Evangelos; Croes, Kris; Bekaert, Joost; Vandenberghe, Geert; Stucchi, Michele; Dehaene, Wim (2016-11)

Templated DSA vias in sub-7 nm circuits: Design strategy and DSA-aware via decomposition

Karageorgos, Ioannis; Ryckaert, Julien; Gronheid, Roel; Tung, Maryann C.; Wong, H.-S. Philip; Karageorgos, Evangelos; Bekaert, Joost; Vandenberghe, Geert; Dehaene, Wim (2016-10)

Design method for the integration of DSA via patterning in sub-7 nm circuits

Karageorgos, Ioannis; Ryckaert, Julien; Croes, Kris; Tung, C. Maryann; Wong, H. -S. Philip; Karageorgos, Evangelos; Gronheid, Roel; Bekaert, Joost; Vandenberghe, Geert; Stucchi, Michele; Dehaene, Wim (2016)

Impact of DSA process variability on circuit performance

Karageorgos, Ioannis; Doise, Jan; Rincon Delgadillo, Paulina; Stucchi, Michele; Baert, Rogier; Gronheid, Roel; Ryckaert, Julien; Vandenberghe, Geert; Dehaene, Wim (2016-10)

Integration of Directed Self-Assembly (DSA) via patterning in sub-7nm interconnects - A designer's perspective

Karageorgos, Ioannis; Dehaene, Wim; Ryckaert, Julien (2016)

Integration of DSA Via Patterning in sub-7 nm Circuits

Karageorgos, Ioannis; Dehaene, Wim (2016)

Design strategy for the integration of DSA vias in sub-7nm interconnects

Karageorgos, Ioannis (2016)

Device breakdown optimization of Al2O3/GaN E-mode MISFETs

Kang, Xuanwu; Wellekens, Dirk; Van Hove, Marleen; De Jaeger, Brice; Ronchi, Nicolo; Wu, Tian-Li; You, Shuzhen; Bakeroot, Benoit; Hu, Jie; Marcon, Denis; Stoffels, Steve; Decoutere, Stefaan (2016)

Unified radio and network control across heterogeneous hardware platforms

Kaminksi, Nicholas; Moerman, Ingrid; Giannoulis, Spilios; Ruckebusch, Peter; Gallo, Pierluigi; Zubow, Anatolij; Leblon, Robin; Seskar, Ivan; Choi, Sunghyun; de Rezende, Jose (2016)

Thermoluminescence spectroscopy study of conjugated polymer films: what can we learn from these measurements?

Kadashchuk, Andriy; Bässler, Heinz (2016)

The defect-centric perspective of device and circuit reliability – From gate oxide defects to circuits

Kaczer, Ben; Franco, Jacopo; Weckx, Pieter; Roussel, Philippe; Simicic, Marko; Putcha, Vamsi; Bury, Erik; Cho, Moon Ju; Degraeve, Robin; Linten, Dimitri; Groeseneken, Guido; Debacker, Peter; Parvais, Bertrand; Raghavan, Praveen; Catthoor, Francky; Rzepa, Gerhard; Waltl, Michael; Goes, Wolfgang; Grasser, Tibor (2016)

imec Publications: Recent submissions

An integrated photonics reservoir computing approach to signal equalization for telecommunications

Uniform large-area slot-die coating of soluble metal oxide semiconductor towards mass production of high-performance TFT backplanes

Performance and reliability impact of copper plasticity in backside TSV-last fabrication process

Design strategy for integrating DSA via patterning in sub-7 nm interconnects

Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits

Templated DSA vias in sub-7 nm circuits: Design strategy and DSA-aware via decomposition

Design method for the integration of DSA via patterning in sub-7 nm circuits

Impact of DSA process variability on circuit performance

Integration of Directed Self-Assembly (DSA) via patterning in sub-7nm interconnects - A designer's perspective

Integration of DSA Via Patterning in sub-7 nm Circuits

Design strategy for the integration of DSA vias in sub-7nm interconnects

Device breakdown optimization of Al2O3/GaN E-mode MISFETs

Unified radio and network control across heterogeneous hardware platforms

Thermoluminescence spectroscopy study of conjugated polymer films: what can we learn from these measurements?

The defect-centric perspective of device and circuit reliability – From gate oxide defects to circuits

Mapping of CMOS FET degradation in bias space - application to DRAM peripheral devices

On the distribution of the FET threshold voltage shifts due to individual charged gate oxide defects

Continuous photoflow synthesis of precision polymers

CVD-Mn/CVD-Ru-based barrier/liner solution for advanced BEOL Cu/low-k interconnects

300mm wafer level CVD-Mn/iodine-CVD-Cu-based metallization study for advanced copper interconnections

imec Publications: Recent submissions

An integrated photonics reservoir computing approach to signal equalization for telecommunications ﻿

Uniform large-area slot-die coating of soluble metal oxide semiconductor towards mass production of high-performance TFT backplanes ﻿

Performance and reliability impact of copper plasticity in backside TSV-last fabrication process ﻿

Design strategy for integrating DSA via patterning in sub-7 nm interconnects ﻿

Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits ﻿

Templated DSA vias in sub-7 nm circuits: Design strategy and DSA-aware via decomposition ﻿

Design method for the integration of DSA via patterning in sub-7 nm circuits ﻿

Impact of DSA process variability on circuit performance ﻿

Integration of Directed Self-Assembly (DSA) via patterning in sub-7nm interconnects - A designer's perspective ﻿

Integration of DSA Via Patterning in sub-7 nm Circuits ﻿

Design strategy for the integration of DSA vias in sub-7nm interconnects ﻿

Device breakdown optimization of Al2O3/GaN E-mode MISFETs ﻿

Unified radio and network control across heterogeneous hardware platforms ﻿

Thermoluminescence spectroscopy study of conjugated polymer films: what can we learn from these measurements? ﻿

The defect-centric perspective of device and circuit reliability – From gate oxide defects to circuits ﻿

Mapping of CMOS FET degradation in bias space - application to DRAM peripheral devices ﻿

On the distribution of the FET threshold voltage shifts due to individual charged gate oxide defects ﻿

Continuous photoflow synthesis of precision polymers ﻿

CVD-Mn/CVD-Ru-based barrier/liner solution for advanced BEOL Cu/low-k interconnects ﻿

300mm wafer level CVD-Mn/iodine-CVD-Cu-based metallization study for advanced copper interconnections ﻿

An integrated photonics reservoir computing approach to signal equalization for telecommunications

Uniform large-area slot-die coating of soluble metal oxide semiconductor towards mass production of high-performance TFT backplanes

Performance and reliability impact of copper plasticity in backside TSV-last fabrication process

Design strategy for integrating DSA via patterning in sub-7 nm interconnects

Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits

Templated DSA vias in sub-7 nm circuits: Design strategy and DSA-aware via decomposition

Design method for the integration of DSA via patterning in sub-7 nm circuits

Impact of DSA process variability on circuit performance

Integration of Directed Self-Assembly (DSA) via patterning in sub-7nm interconnects - A designer's perspective

Integration of DSA Via Patterning in sub-7 nm Circuits

Design strategy for the integration of DSA vias in sub-7nm interconnects

Device breakdown optimization of Al2O3/GaN E-mode MISFETs

Unified radio and network control across heterogeneous hardware platforms

Thermoluminescence spectroscopy study of conjugated polymer films: what can we learn from these measurements?

The defect-centric perspective of device and circuit reliability – From gate oxide defects to circuits

Mapping of CMOS FET degradation in bias space - application to DRAM peripheral devices

On the distribution of the FET threshold voltage shifts due to individual charged gate oxide defects

Continuous photoflow synthesis of precision polymers

CVD-Mn/CVD-Ru-based barrier/liner solution for advanced BEOL Cu/low-k interconnects

300mm wafer level CVD-Mn/iodine-CVD-Cu-based metallization study for advanced copper interconnections