Recently added

Development and implementation of a plated and solderable metallization on 15.6x15.6 cm2 IBC cells

Singh, Sukhvinder; O'Sullivan, Barry; Kyuzo, Manabu; Tous, Loic; Russell, Richard; Bertens, Jurgen; de Wit, Andre; Debucquoy, Maarten; Szlufcik, Jozef; Poortmans, Jef (2015)

Impact of sequential infiltration synthesis on pattern fidelity of DSA lines

Singh, Arjun; Knaepen, Werner; Sayan, Safak; El Otell, Ziad; Chan, BT; Maes, Jan; Gronheid, Roel (2015)

Patterning sub-25nm half-pitch hexagonal arrays of contact holes with chemo-epitaxial DSA guided by ArFi pre-patterns

Singh, Arjun; Chan, BT; Parnell, Doni; Wu, Hengpeng; Lin, Jian; Cao, Yi; Gronheid, Roel (2015)

Impact of thermal budget on the low-frequency noise of DRAM peripheral nMOSFETs

Simoen, Eddy; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; Aoulaiche, Marc; Fazan, Pierre; Na, Hoon Joo; Lee, Sun Ghil; Son, Yunik; Noh, Kyung Bong; Horiguchi, Naoto; Thean, Aaron; Claeys, Cor (2015)

Low frequency noise of advanced memory devices

Simoen, Eddy; Ritzenthaler, Romain; Schram, Tom; Horiguchi, Naoto; Jurczak, Gosia; Thean, Aaron; Claeys, Cor; Aoulaiche, Marc; Spessot, Alessio; Fazan, Pierre (2015)

Increase in oxide trap density due to the implementation of high-k and Al2O3 cap layers in thick-oxide input-output transistors for DRAM applications

Simoen, Eddy; Ritzenthaler, Romain; Cho, Moon Ju; Schram, Tom; Horiguchi, Naoto; Aoulaiche, Marc; Spessot, Alessio; Fazan, Pierre; Claeys, Cor (2015)

On the electrical activity of extended defects in high-mobility channel materials

Simoen, Eddy; Eneman, Geert; Hikavyy, Andriy; Loo, Roger; Gupta, Somya; Merckling, Clement; Alian, AliReza; Schulze, Andreas; Caymax, Matty; Langer, Robert; Barla, Kathy; Claeys, Cor (2015)

Implications of inelastic tunneling on the depth of oxide traps in MOSFETs assessed by RTS or BTI

Simoen, Eddy; Claeys, Cor; Fang, Wen; Luo, Jun; Zhao, Chao (2015)

Noise analysis inadvanced memory devices

Simoen, Eddy; Aoulaiche, Marc; Jurczak, Gosia; Giusi, Gino; Claeys, Cor (2015)

The assessment of border traps in high-mobility channel materials

Simoen, Eddy; Alian, AliReza; Arimura, Hiroaki; Lin, Dennis; Mertens, Hans; Mitard, Jerome; Sioncke, Sonja; Fang, Wen; Luo, Jun; Zhao, Chao; Mocuta, Anda; Collaert, Nadine; Thean, Aaron; Claeys, Cor (2015)

MOSFET variability and reliability characterization array

Simicic, Marko; Putcha, Vamsi; Parvais, Bertrand; Weckx, Pieter; Kaczer, Ben; Groeseneken, Guido; Gielen, Georges; Linten, Dimitri; Thean, Aaron (2015)

Enhanced Ge photoluminescence by increasing the active P doping using high order Ge precursors at lower growth temperatures

Shimura, Yosuke; Srinivasan, Ashwyn; Van Thourhout, Dries; Van Deun, Rik; Pantouvaki, Marianna; Van Campenhout, Joris; Loo, Roger (2015)

Enhancement of active phosphorus concentration in Ge CVD layers in view of group-IV optical interconnections using low temperature in-situ doping and high order Ge precursors

Shimura, Yosuke; Srinivasan, Ashwyn; Van Thourhout, Dries; Van Deun, R.; Pantouvaki, Marianna; Van Campenhout, Joris; Loo, Roger (2015)

Conference contributions: Recent submissions

Development and implementation of a plated and solderable metallization on 15.6x15.6 cm2 IBC cells

Impact of sequential infiltration synthesis on pattern fidelity of DSA lines

Patterning sub-25nm half-pitch hexagonal arrays of contact holes with chemo-epitaxial DSA guided by ArFi pre-patterns

Impact of thermal budget on the low-frequency noise of DRAM peripheral nMOSFETs

Low frequency noise of advanced memory devices

Increase in oxide trap density due to the implementation of high-k and Al2O3 cap layers in thick-oxide input-output transistors for DRAM applications

On the electrical activity of extended defects in high-mobility channel materials

Implications of inelastic tunneling on the depth of oxide traps in MOSFETs assessed by RTS or BTI

Noise analysis inadvanced memory devices

The assessment of border traps in high-mobility channel materials

MOSFET variability and reliability characterization array

Enhanced Ge photoluminescence by increasing the active P doping using high order Ge precursors at lower growth temperatures

Enhancement of active phosphorus concentration in Ge CVD layers in view of group-IV optical interconnections using low temperature in-situ doping and high order Ge precursors

Low temperature in-situ P-doped Ge using Ge2H6 for use in optical applications

At-speed inter-die interconnect test in 2.5D- and 3D-SICs

At-speed testing of inter-die connections of 3D-SICs in the presence of shore logic

At-Speed delay testing of inter-die connections of 2.5D- and 3D-SICs

At-speed delay testing of inter-die connections of 2.5D- and 3D-SICs

At-speed delay testing of inter-die connections of 2.5D- and 3D-SICs

Low optical loss ohmic contacts on heavily doped n-type InGaAs for InP membrabes devices

Conference contributions: Recent submissions

Development and implementation of a plated and solderable metallization on 15.6x15.6 cm2 IBC cells ﻿

Impact of sequential infiltration synthesis on pattern fidelity of DSA lines ﻿

Patterning sub-25nm half-pitch hexagonal arrays of contact holes with chemo-epitaxial DSA guided by ArFi pre-patterns ﻿

Impact of thermal budget on the low-frequency noise of DRAM peripheral nMOSFETs ﻿

Low frequency noise of advanced memory devices ﻿

Increase in oxide trap density due to the implementation of high-k and Al2O3 cap layers in thick-oxide input-output transistors for DRAM applications ﻿

On the electrical activity of extended defects in high-mobility channel materials ﻿

Implications of inelastic tunneling on the depth of oxide traps in MOSFETs assessed by RTS or BTI ﻿

Noise analysis inadvanced memory devices ﻿

The assessment of border traps in high-mobility channel materials ﻿

MOSFET variability and reliability characterization array ﻿

Enhanced Ge photoluminescence by increasing the active P doping using high order Ge precursors at lower growth temperatures ﻿

Enhancement of active phosphorus concentration in Ge CVD layers in view of group-IV optical interconnections using low temperature in-situ doping and high order Ge precursors ﻿

Low temperature in-situ P-doped Ge using Ge2H6 for use in optical applications ﻿

At-speed inter-die interconnect test in 2.5D- and 3D-SICs ﻿

At-speed testing of inter-die connections of 3D-SICs in the presence of shore logic ﻿

At-Speed delay testing of inter-die connections of 2.5D- and 3D-SICs ﻿

At-speed delay testing of inter-die connections of 2.5D- and 3D-SICs ﻿

At-speed delay testing of inter-die connections of 2.5D- and 3D-SICs ﻿

Low optical loss ohmic contacts on heavily doped n-type InGaAs for InP membrabes devices ﻿

Development and implementation of a plated and solderable metallization on 15.6x15.6 cm2 IBC cells

Impact of sequential infiltration synthesis on pattern fidelity of DSA lines

Patterning sub-25nm half-pitch hexagonal arrays of contact holes with chemo-epitaxial DSA guided by ArFi pre-patterns

Impact of thermal budget on the low-frequency noise of DRAM peripheral nMOSFETs

Low frequency noise of advanced memory devices

Increase in oxide trap density due to the implementation of high-k and Al2O3 cap layers in thick-oxide input-output transistors for DRAM applications

On the electrical activity of extended defects in high-mobility channel materials

Implications of inelastic tunneling on the depth of oxide traps in MOSFETs assessed by RTS or BTI

Noise analysis inadvanced memory devices

The assessment of border traps in high-mobility channel materials

MOSFET variability and reliability characterization array

Enhanced Ge photoluminescence by increasing the active P doping using high order Ge precursors at lower growth temperatures

Enhancement of active phosphorus concentration in Ge CVD layers in view of group-IV optical interconnections using low temperature in-situ doping and high order Ge precursors

Low temperature in-situ P-doped Ge using Ge2H6 for use in optical applications

At-speed inter-die interconnect test in 2.5D- and 3D-SICs

At-speed testing of inter-die connections of 3D-SICs in the presence of shore logic

At-Speed delay testing of inter-die connections of 2.5D- and 3D-SICs

At-speed delay testing of inter-die connections of 2.5D- and 3D-SICs

At-speed delay testing of inter-die connections of 2.5D- and 3D-SICs

Low optical loss ohmic contacts on heavily doped n-type InGaAs for InP membrabes devices