Browsing by Author "Hiblot, Gaspard"

Antenna effect in 65nm NMOS devices with 9.5nm thick HfOx gate dielectric

Backside power delivery with a direct 14:1/19:1 high-ratio point-of-load power converter for servers and datacenters

CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark

Characterization of Impact of Vertical Stress on FinFETs

Comparative analysis of the degradation mechanisms in logic and I/O FinFET devices induced by plasma damage

Cumulated charging mechanisms at gate processing in high-kappa first planar NMOS devices

Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node

DIBL-compensated extraction of the channel length modulation coefficient in MOSFETs

Electrical characterization of BEOL plasma-induced damage in bulk FinFET technology

Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster

Factor analysis of plasma-induced damage in bulk FinFET technology

FinFET EOT extraction from accumulation capacitance measurements

Full loop equivalent circuit model for plasma induced damage simulation

Impact of 1 $lm TSV via-last integration on electrical performance of advanced FinFET devices

Impact of local-interconnect to gate overlay on series resistance compensation for saturation velocity extraction

Impact of packaging stress on thinned 6T SRAM die

Impact of Sub-mu m Wafer Thinning on Latch-up Risk in STCO Scaling Era

Impacts of Through-Silicon Vias on Total-Ionizing-Dose Effects and Low-Frequency Noise in FinFETs

Impacts of through-silicon vias on total-ionizing-dose effects and low-frequency noise in FinFETs

In-situ investigation of the impact of externally applied vertical stress on III-V bipolar transistor