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Browsing by Author "Hikavyy, Andriy"

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    15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

    Mitard, Jerome  
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    Witters, Liesbeth  
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    Loo, Roger  
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    Lee, Seung Hun
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    Sun, J.W.
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    Franco, Jacopo  
    Proceedings paper
    2014, Symposium on VLSI Technology, 9/06/2014, p.138-139
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    1mA/μm-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D

    Mitard, Jerome  
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    Witters, Liesbeth  
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    Hellings, Geert  
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    Krom, Raymond
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    Franco, Jacopo  
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    Eneman, Geert  
    Proceedings paper
    2011, Symposium on VLSI Technology, 13/06/2011, p.134-135
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    3D sequential CMOS top tier devices demonstration using a low temperature Smart Cu (TM) Si layer transfer

    Besnard, Guillaume
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    Radu, Ionut
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    Vandooren, Anne  
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    Wu, Zhicheng  
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    Franco, Jacopo  
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    Li, Waikin  
    Proceedings paper
    2021, 26th Silicon Nanoelectronics Workshop, JUN 13, 2021, p.47-48
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    3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters

    Vandooren, Anne  
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    Wu, Zhicheng  
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    Parihar, Narendra  
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    Franco, Jacopo  
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    Parvais, Bertrand  
    Proceedings paper
    2020, IEEE Symposium on VLSI Technology and Circuits, JUN 15-19, 2020
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    3D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability

    Vandooren, Anne  
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    Franco, Jacopo  
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    Parvais, Bertrand  
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    Wu, Zhicheng  
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    Witters, Liesbeth  
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    Walke, Amey  
    Journal article
    2018-11, IEEE Transactions on Electron Devices, (65) 11, p.5165-5171
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    3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

    Vandooren, Anne  
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    Franco, Jacopo  
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    Parvais, Bertrand  
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    Wu, Zhicheng  
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    Witters, Liesbeth  
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    Walke, Amey  
    Proceedings paper
    2018, IEEE Symposium on VLSI Technology, 18/06/2018, p.69-70
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    85nm-wide 1.5mA/μm-ION IFQW SiGe-pFET: raised vs embedded Si0.75Ge0.25 S/D benchmarking and in-depth hole transport study

    Mitard, Jerome  
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    Witters, Liesbeth  
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    Eneman, Geert  
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    Hellings, Geert  
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    Pantisano, Luigi
    Proceedings paper
    2012, Symposium on VLSI Technology - VLSIT, 12/06/2012, p.163-164
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    8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

    Witters, Liesbeth  
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    Takeoka, Shinji
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    Yamaguchi, Shinpei
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    Hikavyy, Andriy  
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    Shamiryan, Denis
    Proceedings paper
    2010, IEEE Symposium on VLSI Technology, 15/06/2010, p.181-182
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    A 2nd generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs

    Mitard, Jerome  
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    Witters, Liesbeth  
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    Sasaki, Yuichiro
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    Arimura, Hiroaki  
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    Schulze, Andreas
    Proceedings paper
    2016-06, IEEE Symposium on VLSI Technology, 13/06/2016, p.34-35
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    A new complementary hetero-junction vertical tunnel-FET integration scheme

    Rooyackers, Rita
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    Vandooren, Anne  
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    Verhulst, Anne  
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    Walke, A.
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    Devriendt, Katia  
    Proceedings paper
    2013, International Electron Devices Meeting - IEDM, 9/12/2013, p.92-95
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    A new method to fabricate Ge nanowires: selective lateral etching of GeSn:P-Ge multi-stacks

    Porret, Clément  
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    Vohra, Anurag  
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    Sebaai, Farid  
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    Douhard, Bastien  
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    Hikavyy, Andriy  
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    Loo, Roger  
    Proceedings paper
    2018, Ultra Clean Processing of Semiconductor Surfaces XIV, 3/09/2018, p.113-120
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    A Statistical Approach for Evaluating the Spatial Distribution and Local Atomic Environment of Dopants Using Atom Probe Tomography

    Lin, Jhao-Rong  
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    Morris, Richard  
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    Scheerder, Jeroen  
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    Hikavyy, Andriy  
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    Porret, Clément  
    Journal article
    2025, MICROSCOPY AND MICROANALYSIS, (31) 6, p.ozaf114
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    Ab initio analysis of defect formation and dopant activation in P and As co-doped Si

    Nakazaki, Nobuya  
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    Rosseel, Erik  
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    Porret, Clément  
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    Hikavyy, Andriy  
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    Loo, Roger  
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    Horiguchi, Naoto  
    Meeting abstract
    2019, 2019 E-MRS Fall Meeting and Exhibit, 16/09/2019
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    Advantage of NW structure in preservation of SRB-induced strain and investigation of off-state leakage in strained stacked Ge NW pFET

    Arimura, Hiroaki  
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    Eneman, Geert  
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    Capogreco, Elena  
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    Witters, Liesbeth  
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    De Keersgieter, An  
    Proceedings paper
    2018, IEEE International Electron Devices Meeting - IEDM, 1/12/2018, p.496-499
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    An in-depth study of high-performing strained germanium nanaowires pFETs

    Mitard, Jerome  
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    Jang, Doyoung  
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    Eneman, Geert  
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    Arimura, Hiroaki  
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    Parvais, Bertrand  
    Proceedings paper
    2018, IEEE Symposium on VLSI Technology, 18/06/2018, p.83-84
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    An investigation of disilane-digermane precursors combination for low temperature SiGe epitaxy

    Hikavyy, Andriy  
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    Zyulkov, Ivan  
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    Loo, Roger  
    Proceedings paper
    2015, the 9th International Conference of Silicon Epitaxy and Heterostructures - ICSI-9, 17/05/2015
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    An investigation of growth and properties of Si capping layers used in advanced SiGe/Ge based pMOS transistors

    Hikavyy, Andriy  
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    Witters, Liesbeth  
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    Mitard, Jerome  
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    Vanherle, Wendy  
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    Vandervorst, Wilfried  
    Meeting abstract
    2012, International Silicon-Germanium Technology and Device Meeting, 4/06/2012
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    Analysis of the pre-epi bake conditions on the defect creation in recessed Si1-xGex S/D junctions

    Bargallo Gonzalez, Mireia
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    Thomas, Nicole
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    Simoen, Eddy  
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    Verheyen, Peter  
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    Hikavyy, Andriy  
    Proceedings paper
    2007, Analytical and Diagnostic Techniques for Semiconductor Materials, Devices, and Processes 7, 7/10/2007, p.47-53
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    Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction tunnel-FETs

    Vandooren, Anne  
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    Rooyackers, Rita
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    Leonelli, Daniele  
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    Hikavyy, Andriy  
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    Devriendt, Katia  
    Journal article
    2013, Solid-State Electronics, 83, p.50-55
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    Application of Cl2 for low temperature etch and epitaxy

    Hikavyy, Andriy  
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    Porret, Clément  
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    Rosseel, Erik  
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    Milenin, Alexey  
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    Loo, Roger  
    Journal article
    2019, Semiconductor Science and Technology, (34) 7, p.74003
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