Browsing by Author "Hikavyy, Andriy"
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Publication 15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process
Proceedings paper2014, Symposium on VLSI Technology, 9/06/2014, p.138-139Publication 1mA/μm-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D
; ; ; ;Krom, Raymond; Proceedings paper2011, Symposium on VLSI Technology, 13/06/2011, p.134-135Publication 3D sequential CMOS top tier devices demonstration using a low temperature Smart Cu (TM) Si layer transfer
Proceedings paper2021, 26th Silicon Nanoelectronics Workshop, JUN 13, 2021, p.47-48Publication 3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters
Proceedings paper2020, IEEE Symposium on VLSI Technology and Circuits, JUN 15-19, 2020Publication 3D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability
; ; ; ; ; Journal article2018-11, IEEE Transactions on Electron Devices, (65) 11, p.5165-5171Publication 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability
; ; ; ; ; Proceedings paper2018, IEEE Symposium on VLSI Technology, 18/06/2018, p.69-70Publication 85nm-wide 1.5mA/μm-ION IFQW SiGe-pFET: raised vs embedded Si0.75Ge0.25 S/D benchmarking and in-depth hole transport study
Proceedings paper2012, Symposium on VLSI Technology - VLSIT, 12/06/2012, p.163-164Publication 8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS
Proceedings paper2010, IEEE Symposium on VLSI Technology, 15/06/2010, p.181-182Publication A 2nd generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs
Proceedings paper2016-06, IEEE Symposium on VLSI Technology, 13/06/2016, p.34-35Publication A new complementary hetero-junction vertical tunnel-FET integration scheme
Proceedings paper2013, International Electron Devices Meeting - IEDM, 9/12/2013, p.92-95Publication A new method to fabricate Ge nanowires: selective lateral etching of GeSn:P-Ge multi-stacks
Proceedings paper2018, Ultra Clean Processing of Semiconductor Surfaces XIV, 3/09/2018, p.113-120Publication A Statistical Approach for Evaluating the Spatial Distribution and Local Atomic Environment of Dopants Using Atom Probe Tomography
Journal article2025, MICROSCOPY AND MICROANALYSIS, (31) 6, p.ozaf114Publication Ab initio analysis of defect formation and dopant activation in P and As co-doped Si
; ; ; ; ; Meeting abstract2019, 2019 E-MRS Fall Meeting and Exhibit, 16/09/2019Publication Advantage of NW structure in preservation of SRB-induced strain and investigation of off-state leakage in strained stacked Ge NW pFET
Proceedings paper2018, IEEE International Electron Devices Meeting - IEDM, 1/12/2018, p.496-499Publication An in-depth study of high-performing strained germanium nanaowires pFETs
Proceedings paper2018, IEEE Symposium on VLSI Technology, 18/06/2018, p.83-84Publication An investigation of disilane-digermane precursors combination for low temperature SiGe epitaxy
Proceedings paper2015, the 9th International Conference of Silicon Epitaxy and Heterostructures - ICSI-9, 17/05/2015Publication An investigation of growth and properties of Si capping layers used in advanced SiGe/Ge based pMOS transistors
Meeting abstract2012, International Silicon-Germanium Technology and Device Meeting, 4/06/2012Publication Analysis of the pre-epi bake conditions on the defect creation in recessed Si1-xGex S/D junctions
Proceedings paper2007, Analytical and Diagnostic Techniques for Semiconductor Materials, Devices, and Processes 7, 7/10/2007, p.47-53Publication Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction tunnel-FETs
Journal article2013, Solid-State Electronics, 83, p.50-55Publication Application of Cl2 for low temperature etch and epitaxy
Journal article2019, Semiconductor Science and Technology, (34) 7, p.74003