Browsing by Author "Huynh Bao, Trong"
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Publication 12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices
; ; ; ; Huynh Bao, TrongProceedings paper2019, 2019 Symposium on VLSI Technology, 9/06/2019, p.T15-1Publication A comprehensive benchmark and optimization of 5-nm lateral and vertical GAA 6T-SRAMs
Journal article2016, IEEE Transactions on Electron Devices, (63) 2, p.643-651Publication Challenges and opportunities for vertical nanowire FETs: device design and fabrication
Proceedings paper2018, 50th International Conference on Solid State Devices and Materials - SSDM, 9/09/2018, p.159-160Publication Challenges and opportunities of vertical FET devices using 3D circuit design layouts
Proceedings paper2016, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference - S3S, 10/10/2016, p.1-3Publication Challenges on surface conditioning in 3D device architectures: triple-gate FinFETs, gate-all-around lateral and vertical nanowire FETs
Proceedings paper2017, 232nd ECS Fall Meeting - 15th International Symposium on Semiconductor Cleaning Science and Technology - SCST15, 1/10/2017, p.3-20Publication Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies
; ; ; ; Proceedings paper2014-09, 44th European Solid-State Device Research Conference - ESSDERC, 22/09/2014, p.102-105Publication Cross-layer design and analysis of al ow power, high density STT-MRAM for embedded systems
Proceedings paper2017, 2017 IEEE International Symposium of Circuits and Systems - ISCAS, 28/05/2017, p.1-4Publication Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM
Proceedings paper2015, International Conference on IC Design and Technology - ICICDT, 1/06/2015, p.1-4Publication DTCO and TCAD for a 12 layer-EUV ultra-scaled surrounding gate transistor 6T-SRAM
Proceedings paper2018, 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 24/09/2018, p.45-48Publication Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node
; ; ; Proceedings paper2018, IEEE International Electron Devices Meeting - IEDM, 1/12/2018, p.420-423Publication Gate-All-Around nanowire & nanosheet FETs for advanced, ultra-scaled technologies (Keynote)
Meeting abstract2020, Symposium H02 - "Advanced CMOS-Compatible Semiconductor Devices 19" of the 237th ECS Meeting, 10/05/2020, p.1396Publication Heterogeneous nano- to wide-scale co-integration of beyond-Si and Si CMOS devices to enhance future electronics
Proceedings paper2015, Silicon Compatible Materials, and Technologies for Advanced Integrated Processes, Circuits and Emerging Applications 5, 29/06/2015, p.3-14Publication Heterogeneous nano-electronic devices enabled by monolithic integration of IIIV, Ge, and Si to expand future CMOS functionality
Proceedings paper2014, Nanotech: Advanced Materials and Applications, 15/06/2014, p.588-591Publication Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells
Proceedings paper2016, IEEE Symposium on VLSI Technology, 13/06/2016, p.138-139Publication Lateral versus vertical gate-all-around FETs for beyond 7nm technologies
Proceedings paper2014, 72nd Device Research Conference - DRC, 22/06/2014, p.133-134Publication Nanowire & nanosheet FETs for ultra-scaled, hgh-density logic and memory applications
Journal article2020, Solid-State Electronics, 168, p.107736Publication Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications
Proceedings paper2019, 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 1/04/2019, p.1-4Publication Process, circuit and system co-optimization of wafer level co-integrated FinFET with vertical nanosheet selector for STT-MRAM applications
Proceedings paper2019, 2019 56th ACM/IEEE Design Automation Conference (DAC), 2/06/2019, p.1-6Publication SRAM designs for 5nm node and beyond: opportunities and challenges
Meeting abstract2017, IEEE International Conference on IC Design and Technology - ICICDT, 22/05/2017, p.1-4Publication Statistical timing analysis considering device and interconnect variability for BEOL requirements in the 5-nm node and beyond
Journal article2017-05, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (25) 5, p.1669-1680