Browsing by Author "Kukner, Halil"

Bias temperature instability analysis in SRAM decoder

Bias temperature instability analysis of FinFET based SRAM cells

Bias Temperature Instability in CMOS Digital Circuits from Planar to FinFET Nodes

BTI impact on logical gates in nano-scale CMOS technology

BTI reliability from planar to FinFET nodes: Will the next node be more or less reliable?

Comparison of reaction-diffusion and atomistic trap-based BTI models for logic gates

Defect-based methodology for workload-dependent circuit lifetime projections – application to SRAM

Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology

Estimation of sense amplifier offset voltage degradation due to zero- and run-time variability

Impact of duty factor, stress stimuli, and gate drive strength on gate delay degradation with an atomistic trap-based BTI model

Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model

Impact of partial resistive defects and bias temperature instability on SRAM decoder reliability

Incorporating parameter variations in BTI impact on nano-scale logical gate analysis

Integral Impact of BTI, PVT-variation and Workload on SRAM Sense Amplifier

Modelling and mitigation of time-zero variability in sub-16nm FinFET-based STT-MRAM memories

NBTI aging on 32-bit adders in the downscaling planar FET technology nodes

Non-Monte-Carlo methodology for high-sigma simulations of circuits under workload-dependent BTI degradation – application to 6T SRAM

Scaling of BTI reliability in presence of Time-zero Variability – Pathfinding from planar FET to advanced 3-D FinFET nodes

The defect-centric perspective of device and circuit reliability – from individual defects to circuits

The impact of process variation and stochastic aging in nanoscale VLSI