Browsing by Author "Luhn, Ole"
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Publication A new scaled through Si via with polymer fill for 3D wafer level packaging
Proceedings paper2008, International Conference on Solid State Devices and Materials - SSDM, 23/09/2008, p.52-53Publication Additive influence on filling microvias with copper
Oral presentation2008, Gordon Research ConferencePublication Barrier and seed layer coverage in 3D structures with different aspect ratios using sputtering and ALD proecesses
Journal article2008, Microelectronic Engineering, (85) 10, p.1947-1951Publication Changing superfilling mode for copper electrodeposition in blind holes from differential inhibition to differential acceleration
Journal article2009, Electrochemical and Solid-State Letters, (12) 5, p.D39-D41Publication Characteristics of copper electrodeposits on featureless substrates and in microvias with aspect ratio up to 10
Meeting abstract2009, 215th Electrochemical Society Spring Meeting, 24/05/2009, p.997Publication Copper plating for 3D interconnects
Journal article2011, Microelectronic Engineering, (88) 5, p.701-704Publication Copper plating for 3D interconnects
Meeting abstract2009, 216th ECS Meeting, 4/10/2009, p.2779Publication Copper plating for 3d interconnects
Proceedings paper2010, Processing, Materials, and Integration of Damascene and 3D Interconnects, 4/10/2009, p.119-125Publication Cu electrodeposition for Through-Silicon Via Technology
Meeting abstract2009, 215th Electrochemical Society Spring Meeting, 24/05/2009, p.990Publication Cu Plating of Through-Si Vias for 3D-Stacked Integrated Circuits
Proceedings paper2009, Materials and Technologies for 3-D Integration, 1/12/2008, p.1112-E03-06Publication Cu plating of through-Si vias for 3D-stacked integrated circuits
Oral presentation2008, MRS Fall Meeting Symposium E: Materials and Technologies for 3-D IntegrationPublication Electrodeposition for 3D integration
Proceedings paper2010, Symposium " Galvanik " Eine etablierte Technik innovativ angewendet, 25/11/2010, p.31-36Publication Electrodeposition for 3D integration. Investigating copper electrodeposition for 'through-silicon via' applications
Luhn, OlePHD thesis2009-12Publication Filling of microvia with an aspect ratio of 5 by copper electrodeposition
Journal article2009, Electrochimica Acta, (54) 9, p.2504-2508Publication High aspect ratio via metallization for 3D integration using CVD TiN barrier and electrografted Cu seed
Journal article2008, Microelectronic Engineering, (85) 10, p.1957-1961Publication Improving the copper electroplating process for 3D-stacked integrated circuits
Journal article2008, Semiconductor Manufacturing China, 5, p.26-28Publication Influence of annealing conditions on the mechanical and microstructural behavior of electroplated Cu-TSV
Journal article2010, Journal of Micromechanics and Microengineering, (20) 4, p.45032Publication Leveling of microvias for wafer level packaging
Proceedings paper2007-05, Electrochemical Processing in ULSI and MEMS 3, 6/05/2007, p.123-133Publication Metallization of 3D via structures in silicon for interconnect technology
Meeting abstract2008, 17th Workshop Materials for Advanced Metallization, 2/03/2008, p.39-40