Browsing by Author "Maenhoudt, Mireille"

248nm and 193nm lithography for damascene patterning

30-nm half-pitch metal patterning using MotifTM critical dimension shrink technique and double patterning

30nm half-pitch metal patterning using MotifTM CD shrink technique and double patterning

A 0.314mm2 6T-SRAM cell built with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography

A methodology for double patterning compliant split and design

A methodology for the characterization of topography induced immersion bubble defects

Advanced optical lithography: double patterning options for 32 and 22nm node

Advanced solutions for copper and low k technology

Alternative double patterning processes: ready for (sub) 32nm hp

Alternative process schemes for double patterning that eliminate the intermediate etch step

An automated method for overlay sample plan optimization based on spatial variation modeling

Applying a thin imaging resist system to substrates with topography

Back-end, low-k dielectric compatible resist rework procedure

CD control comparison of step & repeat versus step & scan DUV lithography for sub-0.25 μm gate printing

Characterisation and integration feasibility of JSR's low-k dielectric LKD-5109

Characterisation of JSR's spin-on hardmask FF-02

Characterization of PVD TaN and ALD WNxCy copper diffusion barriers on a porous CVD low-k material

Checking design conformance and optimizing manufacturability using automated double-patterning decomposition

CMOS 32nm technology node: business as usual for interconnect damascene patterning?

Comparison of LFLE and LELE manufacturability